[Exegesis][RISCV] Skip some of the tests under expensive checks

Under expensive checks, some of the tests will fail to pass the
MachineVerifier. It's because right after a snippet is generated, its VL
operand (if it's a register) is assigned a physical register. While
we'll replace it with virtual register in RISCVExegesisPreprocessing,
it's technically violating RISCVInstrInfo's validation rule.
Under normal circumstances, this won't trigger a MachineVerifier failure
because the codegen pipeline doesn't validate the code until the very
end -- which is not the case under EXPENSIVE_CHECKS where
MachineVerifierPass is sprinkled here and there.

This is really caused by the fact that RISCV exegesis has an odd
"codegen" Pass pipeline. And I don't have a good solution yet, so I'm
surpressing these tests under EXPENSIVE_CHECKS.

Author: mshockwave

llvm/test/tools/llvm-exegesis/RISCV/rvv/explicit-sew.test

@@ -1,5 +1,6 @@
 # RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVFWREDUSUM_VS_M1_E32 \
 # RUN:    --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s
+# UNSUPPORTED: expensive_checks
 
 # Make sure none of the config has SEW other than e32
 # CHECK: PseudoVFWREDUSUM_VS_M1_E32

llvm/test/tools/llvm-exegesis/RISCV/rvv/skip-rm.test

@@ -2,6 +2,7 @@
 # RUN:    --riscv-enumerate-rounding-modes=false --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s --check-prefix=VX
 # RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-x280 -benchmark-phase=assemble-measured-code --mode=latency --opcode-name=PseudoVFADD_VFPR16_M1_E16 \
 # RUN:    --riscv-enumerate-rounding-modes=false --max-configs-per-opcode=1000 --min-instructions=100 | FileCheck %s --check-prefix=FP
+# UNSUPPORTED: expensive_checks
 
 # VX: PseudoVAADDU_VV_M1
 # VX: VXRM: rnu

llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew-zvk.test

@@ -19,6 +19,7 @@
 # RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p670 -benchmark-phase=assemble-measured-code --mode=inverse_throughput \
 # RUN:    --opcode-name=PseudoVSM3C_VI_M1 --max-configs-per-opcode=1000 --min-instructions=100 | \
 # RUN:    FileCheck %s --allow-empty --check-prefix=EMPTY
+# UNSUPPORTED: expensive_checks
 
 # Most vector crypto only supports SEW=32, except Zvknhb which also supports SEW=64
 # ZVK-NOT: SEW: e{{(8|16)}}

llvm/test/tools/llvm-exegesis/RISCV/rvv/valid-sew.test

@@ -9,6 +9,7 @@
 # RUN: llvm-exegesis -mtriple=riscv64 -mcpu=sifive-p470 -benchmark-phase=assemble-measured-code --mode=latency \
 # RUN:    --opcode-name=PseudoVFREDUSUM_VS_M1_E16 --max-configs-per-opcode=1000 --min-instructions=100 | \
 # RUN:    FileCheck %s --check-prefix=VFRED --allow-empty
+# UNSUPPORTED: expensive_checks
 
 # Make sure only the supported SEWs are generated for fractional LMUL.
 # FRAC-LMUL: PseudoVMUL_VV_MF4_MASK