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AMDGPU: Infer no-agpr usage in AMDGPUAttributor (#85948)
SIMachineFunctionInfo has a scan of the function body for inline asm which may use AGPRs, or callees in SIMachineFunctionInfo. Move this into the attributor, so it actually works interprocedurally. Could probably avoid most of the test churn if this bothered to avoid adding this on subtargets without AGPRs. We should also probably try to delete the MIR scan in usesAGPRs but it seems to be trickier to eliminate.
1 parent 1404640 commit b6b703b

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lines changed

‎llvm/docs/AMDGPUUsage.rst

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Original file line numberDiff line numberDiff line change
@@ -1454,6 +1454,11 @@ The AMDGPU backend supports the following LLVM IR attributes.
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CLANG attribute [CLANG-ATTR]_. Clang only emits this attribute when all
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the three numbers are >= 1.
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"amdgpu-no-agpr" Indicates the function will not require allocating AGPRs. This is only
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relevant on subtargets with AGPRs. The behavior is undefined if a
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function which requires AGPRs is reached through any function marked
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with this attribute.
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======================================= ==========================================================
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Calling Conventions

‎llvm/lib/Target/AMDGPU/AMDGPUAttributor.cpp

Lines changed: 94 additions & 2 deletions
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@@ -918,6 +918,96 @@ AAAMDWavesPerEU &AAAMDWavesPerEU::createForPosition(const IRPosition &IRP,
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llvm_unreachable("AAAMDWavesPerEU is only valid for function position");
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}
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static bool inlineAsmUsesAGPRs(const InlineAsm *IA) {
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for (const auto &CI : IA->ParseConstraints()) {
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for (StringRef Code : CI.Codes) {
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Code.consume_front("{");
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if (Code.starts_with("a"))
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return true;
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}
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}
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return false;
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}
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struct AAAMDGPUNoAGPR
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: public IRAttribute<Attribute::NoUnwind,
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StateWrapper<BooleanState, AbstractAttribute>,
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AAAMDGPUNoAGPR> {
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AAAMDGPUNoAGPR(const IRPosition &IRP, Attributor &A) : IRAttribute(IRP) {}
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static AAAMDGPUNoAGPR &createForPosition(const IRPosition &IRP,
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Attributor &A) {
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if (IRP.getPositionKind() == IRPosition::IRP_FUNCTION)
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return *new (A.Allocator) AAAMDGPUNoAGPR(IRP, A);
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llvm_unreachable("AAAMDGPUNoAGPR is only valid for function position");
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}
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void initialize(Attributor &A) override {
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Function *F = getAssociatedFunction();
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if (F->hasFnAttribute("amdgpu-no-agpr"))
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indicateOptimisticFixpoint();
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}
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const std::string getAsStr(Attributor *A) const override {
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return getAssumed() ? "amdgpu-no-agpr" : "amdgpu-maybe-agpr";
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}
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void trackStatistics() const override {}
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ChangeStatus updateImpl(Attributor &A) override {
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// TODO: Use AACallEdges, but then we need a way to inspect asm edges.
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auto CheckForNoAGPRs = [&](Instruction &I) {
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const auto &CB = cast<CallBase>(I);
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const Value *CalleeOp = CB.getCalledOperand();
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const Function *Callee = dyn_cast<Function>(CalleeOp);
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if (!Callee) {
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if (const InlineAsm *IA = dyn_cast<InlineAsm>(CalleeOp))
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return !inlineAsmUsesAGPRs(IA);
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return false;
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}
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// Some intrinsics may use AGPRs, but if we have a choice, we are not
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// required to use AGPRs.
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if (Callee->isIntrinsic())
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return true;
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// TODO: Handle callsite attributes
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const auto *CalleeInfo = A.getAAFor<AAAMDGPUNoAGPR>(
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*this, IRPosition::function(*Callee), DepClassTy::REQUIRED);
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return CalleeInfo && CalleeInfo->getAssumed();
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};
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bool UsedAssumedInformation = false;
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if (!A.checkForAllCallLikeInstructions(CheckForNoAGPRs, *this,
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UsedAssumedInformation))
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return indicatePessimisticFixpoint();
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return ChangeStatus::UNCHANGED;
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}
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ChangeStatus manifest(Attributor &A) override {
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if (!getAssumed())
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return ChangeStatus::UNCHANGED;
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LLVMContext &Ctx = getAssociatedFunction()->getContext();
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return A.manifestAttrs(getIRPosition(),
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{Attribute::get(Ctx, "amdgpu-no-agpr")});
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}
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const std::string getName() const override { return "AAAMDGPUNoAGPR"; }
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const char *getIdAddr() const override { return &ID; }
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/// This function should return true if the type of the \p AA is
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/// AAAMDGPUNoAGPRs
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static bool classof(const AbstractAttribute *AA) {
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return (AA->getIdAddr() == &ID);
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}
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static const char ID;
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};
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const char AAAMDGPUNoAGPR::ID = 0;
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static void addPreloadKernArgHint(Function &F, TargetMachine &TM) {
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const GCNSubtarget &ST = TM.getSubtarget<GCNSubtarget>(F);
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for (unsigned I = 0;
@@ -946,8 +1036,9 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM) {
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DenseSet<const char *> Allowed(
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{&AAAMDAttributes::ID, &AAUniformWorkGroupSize::ID,
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&AAPotentialValues::ID, &AAAMDFlatWorkGroupSize::ID,
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&AAAMDWavesPerEU::ID, &AACallEdges::ID, &AAPointerInfo::ID,
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&AAPotentialConstantValues::ID, &AAUnderlyingObjects::ID});
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&AAAMDWavesPerEU::ID, &AAAMDGPUNoAGPR::ID, &AACallEdges::ID,
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&AAPointerInfo::ID, &AAPotentialConstantValues::ID,
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&AAUnderlyingObjects::ID});
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AttributorConfig AC(CGUpdater);
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AC.Allowed = &Allowed;
@@ -963,6 +1054,7 @@ static bool runImpl(Module &M, AnalysisGetter &AG, TargetMachine &TM) {
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if (!F.isIntrinsic()) {
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A.getOrCreateAAFor<AAAMDAttributes>(IRPosition::function(F));
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A.getOrCreateAAFor<AAUniformWorkGroupSize>(IRPosition::function(F));
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A.getOrCreateAAFor<AAAMDGPUNoAGPR>(IRPosition::function(F));
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CallingConv::ID CC = F.getCallingConv();
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if (!AMDGPU::isEntryFunctionCC(CC)) {
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A.getOrCreateAAFor<AAAMDFlatWorkGroupSize>(IRPosition::function(F));

‎llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 1 addition & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -748,35 +748,7 @@ bool SIMachineFunctionInfo::initializeBaseYamlFields(
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}
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bool SIMachineFunctionInfo::mayUseAGPRs(const Function &F) const {
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for (const BasicBlock &BB : F) {
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for (const Instruction &I : BB) {
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const auto *CB = dyn_cast<CallBase>(&I);
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if (!CB)
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continue;
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if (CB->isInlineAsm()) {
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const InlineAsm *IA = dyn_cast<InlineAsm>(CB->getCalledOperand());
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for (const auto &CI : IA->ParseConstraints()) {
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for (StringRef Code : CI.Codes) {
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Code.consume_front("{");
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if (Code.starts_with("a"))
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return true;
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}
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}
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continue;
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}
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const Function *Callee =
770-
dyn_cast<Function>(CB->getCalledOperand()->stripPointerCasts());
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if (!Callee)
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return true;
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774-
if (Callee->getIntrinsicID() == Intrinsic::not_intrinsic)
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return true;
776-
}
777-
}
778-
779-
return false;
751+
return !F.hasFnAttribute("amdgpu-no-agpr");
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}
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782754
bool SIMachineFunctionInfo::usesAGPRs(const MachineFunction &MF) const {

‎llvm/test/CodeGen/AMDGPU/addrspacecast-constantexpr.ll

Lines changed: 3 additions & 3 deletions
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@@ -233,9 +233,9 @@ attributes #1 = { nounwind }
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; AKF_HSA: attributes #[[ATTR1]] = { nounwind }
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;.
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; ATTRIBUTOR_HSA: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
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; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
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; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
238-
; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
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; ATTRIBUTOR_HSA: attributes #[[ATTR1]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
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; ATTRIBUTOR_HSA: attributes #[[ATTR2]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
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; ATTRIBUTOR_HSA: attributes #[[ATTR3]] = { nounwind "amdgpu-no-agpr" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
239239
;.
240240
; AKF_HSA: [[META0:![0-9]+]] = !{i32 1, !"amdhsa_code_object_version", i32 500}
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;.

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