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KanRobertKanRobert
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[X86][CodeGen] Not emit mr_ND if rr_ND is commutable
This gives us more chance to compress instruction in X86CompressEVEX.cpp b/c mr_ND is not a candidate of instructions to be compressed while rm_ND is.
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6 files changed

+66
-52
lines changed

6 files changed

+66
-52
lines changed

‎llvm/lib/Target/X86/X86InstrArithmetic.td

Lines changed: 30 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -756,10 +756,11 @@ multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
756756
def 32mr : BinOpMR_MF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
757757
def 64mr : BinOpMR_MF<BaseOpc, mnemonic, Xi64, opnode>;
758758
let Predicates = [HasNDD, In64BitMode] in {
759-
def 8mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi8 , opnode>;
760-
def 16mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi16, opnode>, PD;
761-
def 32mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi32, opnode>;
762-
def 64mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi64, opnode>;
759+
defvar node = !if(!eq(CommutableRR, 0), opnode, null_frag);
760+
def 8mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi8 , node>;
761+
def 16mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi16, node>, PD;
762+
def 32mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi32, node>;
763+
def 64mr_ND : BinOpMR_RF<BaseOpc, mnemonic, Xi64, node>;
763764
def 8mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi8>, EVEX_NF;
764765
def 16mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi16>, EVEX_NF, PD;
765766
def 32mr_NF_ND : BinOpMR_R<BaseOpc, mnemonic, Xi32>, EVEX_NF;
@@ -944,10 +945,11 @@ multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
944945
def 32mr : BinOpMRF_MF<BaseOpc, mnemonic, Xi32, opnode>, OpSize32;
945946
def 64mr : BinOpMRF_MF<BaseOpc, mnemonic, Xi64, opnode>;
946947
let Predicates = [HasNDD, In64BitMode] in {
947-
def 8mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi8 , opnode>;
948-
def 16mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi16, opnode>, PD;
949-
def 32mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi32, opnode>;
950-
def 64mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi64, opnode>;
948+
defvar node = !if(!eq(CommutableRR, 0), opnode, null_frag);
949+
def 8mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi8 , node>;
950+
def 16mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi16, node>, PD;
951+
def 32mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi32, node>;
952+
def 64mr_ND : BinOpMRF_RF<BaseOpc, mnemonic, Xi64, node>;
951953
}
952954
let Predicates = [In64BitMode] in {
953955
def 8mr_EVEX : BinOpMRF_MF<BaseOpc, mnemonic, Xi8 , null_frag>, PL;
@@ -1108,14 +1110,26 @@ let isCompare = 1 in {
11081110

11091111
// Patterns to recognize loads on the LHS of an ADC. We can't make X86adc_flag
11101112
// commutable since it has EFLAGs as an input.
1111-
def : Pat<(X86adc_flag (loadi8 addr:$src2), GR8:$src1, EFLAGS),
1112-
(ADC8rm GR8:$src1, addr:$src2)>;
1113-
def : Pat<(X86adc_flag (loadi16 addr:$src2), GR16:$src1, EFLAGS),
1114-
(ADC16rm GR16:$src1, addr:$src2)>;
1115-
def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
1116-
(ADC32rm GR32:$src1, addr:$src2)>;
1117-
def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
1118-
(ADC64rm GR64:$src1, addr:$src2)>;
1113+
let Predicates = [NoNDD] in {
1114+
def : Pat<(X86adc_flag (loadi8 addr:$src2), GR8:$src1, EFLAGS),
1115+
(ADC8rm GR8:$src1, addr:$src2)>;
1116+
def : Pat<(X86adc_flag (loadi16 addr:$src2), GR16:$src1, EFLAGS),
1117+
(ADC16rm GR16:$src1, addr:$src2)>;
1118+
def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
1119+
(ADC32rm GR32:$src1, addr:$src2)>;
1120+
def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
1121+
(ADC64rm GR64:$src1, addr:$src2)>;
1122+
}
1123+
let Predicates = [HasNDD] in {
1124+
def : Pat<(X86adc_flag (loadi8 addr:$src2), GR8:$src1, EFLAGS),
1125+
(ADC8rm_ND GR8:$src1, addr:$src2)>;
1126+
def : Pat<(X86adc_flag (loadi16 addr:$src2), GR16:$src1, EFLAGS),
1127+
(ADC16rm_ND GR16:$src1, addr:$src2)>;
1128+
def : Pat<(X86adc_flag (loadi32 addr:$src2), GR32:$src1, EFLAGS),
1129+
(ADC32rm_ND GR32:$src1, addr:$src2)>;
1130+
def : Pat<(X86adc_flag (loadi64 addr:$src2), GR64:$src1, EFLAGS),
1131+
(ADC64rm_ND GR64:$src1, addr:$src2)>;
1132+
}
11191133

11201134
// Patterns to recognize RMW ADC with loads in operand 1.
11211135
def : Pat<(store (X86adc_flag GR8:$src, (loadi8 addr:$dst), EFLAGS),

‎llvm/test/CodeGen/X86/apx/adc.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,7 @@ define i8 @adc8mr(i8 %a, ptr %ptr, i8 %x, i8 %y) nounwind {
211211
; CHECK-LABEL: adc8mr:
212212
; CHECK: # %bb.0:
213213
; CHECK-NEXT: cmpb %dl, %cl # encoding: [0x38,0xd1]
214-
; CHECK-NEXT: adcb %dil, (%rsi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x10,0x3e]
214+
; CHECK-NEXT: adcb (%rsi), %dil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x12,0x3e]
215215
; CHECK-NEXT: retq # encoding: [0xc3]
216216
%b = load i8, ptr %ptr
217217
%s = add i8 %b, %a
@@ -225,7 +225,7 @@ define i16 @adc16mr(i16 %a, ptr %ptr, i16 %x, i16 %y) nounwind {
225225
; CHECK-LABEL: adc16mr:
226226
; CHECK: # %bb.0:
227227
; CHECK-NEXT: cmpw %dx, %cx # encoding: [0x66,0x39,0xd1]
228-
; CHECK-NEXT: adcw %di, (%rsi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x11,0x3e]
228+
; CHECK-NEXT: adcw (%rsi), %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x13,0x3e]
229229
; CHECK-NEXT: retq # encoding: [0xc3]
230230
%b = load i16, ptr %ptr
231231
%s = add i16 %b, %a
@@ -239,7 +239,7 @@ define i32 @adc32mr(i32 %a, ptr %ptr, i32 %x, i32 %y) nounwind {
239239
; CHECK-LABEL: adc32mr:
240240
; CHECK: # %bb.0:
241241
; CHECK-NEXT: cmpl %edx, %ecx # encoding: [0x39,0xd1]
242-
; CHECK-NEXT: adcl %edi, (%rsi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x11,0x3e]
242+
; CHECK-NEXT: adcl (%rsi), %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x13,0x3e]
243243
; CHECK-NEXT: retq # encoding: [0xc3]
244244
%b = load i32, ptr %ptr
245245
%s = add i32 %b, %a
@@ -253,7 +253,7 @@ define i64 @adc64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
253253
; CHECK-LABEL: adc64mr:
254254
; CHECK: # %bb.0:
255255
; CHECK-NEXT: cmpq %rdx, %rcx # encoding: [0x48,0x39,0xd1]
256-
; CHECK-NEXT: adcq %rdi, (%rsi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x11,0x3e]
256+
; CHECK-NEXT: adcq (%rsi), %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x13,0x3e]
257257
; CHECK-NEXT: retq # encoding: [0xc3]
258258
%b = load i64, ptr %ptr
259259
%s = add i64 %b, %a

‎llvm/test/CodeGen/X86/apx/add.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -246,12 +246,12 @@ entry:
246246
define i8 @add8mr(ptr %a, i8 noundef %b) {
247247
; CHECK-LABEL: add8mr:
248248
; CHECK: # %bb.0: # %entry
249-
; CHECK-NEXT: addb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x00,0x37]
249+
; CHECK-NEXT: addb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x02,0x37]
250250
; CHECK-NEXT: retq # encoding: [0xc3]
251251
;
252252
; NF-LABEL: add8mr:
253253
; NF: # %bb.0: # %entry
254-
; NF-NEXT: {nf} addb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x00,0x37]
254+
; NF-NEXT: {nf} addb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x02,0x37]
255255
; NF-NEXT: retq # encoding: [0xc3]
256256
entry:
257257
%t= load i8, ptr %a
@@ -262,12 +262,12 @@ entry:
262262
define i16 @add16mr(ptr %a, i16 noundef %b) {
263263
; CHECK-LABEL: add16mr:
264264
; CHECK: # %bb.0: # %entry
265-
; CHECK-NEXT: addw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x01,0x37]
265+
; CHECK-NEXT: addw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x03,0x37]
266266
; CHECK-NEXT: retq # encoding: [0xc3]
267267
;
268268
; NF-LABEL: add16mr:
269269
; NF: # %bb.0: # %entry
270-
; NF-NEXT: {nf} addw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x01,0x37]
270+
; NF-NEXT: {nf} addw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x03,0x37]
271271
; NF-NEXT: retq # encoding: [0xc3]
272272
entry:
273273
%t= load i16, ptr %a
@@ -278,12 +278,12 @@ entry:
278278
define i32 @add32mr(ptr %a, i32 noundef %b) {
279279
; CHECK-LABEL: add32mr:
280280
; CHECK: # %bb.0: # %entry
281-
; CHECK-NEXT: addl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x01,0x37]
281+
; CHECK-NEXT: addl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x03,0x37]
282282
; CHECK-NEXT: retq # encoding: [0xc3]
283283
;
284284
; NF-LABEL: add32mr:
285285
; NF: # %bb.0: # %entry
286-
; NF-NEXT: {nf} addl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x01,0x37]
286+
; NF-NEXT: {nf} addl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x03,0x37]
287287
; NF-NEXT: retq # encoding: [0xc3]
288288
entry:
289289
%t= load i32, ptr %a
@@ -294,12 +294,12 @@ entry:
294294
define i64 @add64mr(ptr %a, i64 noundef %b) {
295295
; CHECK-LABEL: add64mr:
296296
; CHECK: # %bb.0: # %entry
297-
; CHECK-NEXT: addq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x01,0x37]
297+
; CHECK-NEXT: addq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x03,0x37]
298298
; CHECK-NEXT: retq # encoding: [0xc3]
299299
;
300300
; NF-LABEL: add64mr:
301301
; NF: # %bb.0: # %entry
302-
; NF-NEXT: {nf} addq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x01,0x37]
302+
; NF-NEXT: {nf} addq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x03,0x37]
303303
; NF-NEXT: retq # encoding: [0xc3]
304304
entry:
305305
%t= load i64, ptr %a

‎llvm/test/CodeGen/X86/apx/and.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -248,12 +248,12 @@ entry:
248248
define i8 @and8mr(ptr %a, i8 noundef %b) {
249249
; CHECK-LABEL: and8mr:
250250
; CHECK: # %bb.0: # %entry
251-
; CHECK-NEXT: andb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x20,0x37]
251+
; CHECK-NEXT: andb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x22,0x37]
252252
; CHECK-NEXT: retq # encoding: [0xc3]
253253
;
254254
; NF-LABEL: and8mr:
255255
; NF: # %bb.0: # %entry
256-
; NF-NEXT: {nf} andb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x20,0x37]
256+
; NF-NEXT: {nf} andb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x22,0x37]
257257
; NF-NEXT: retq # encoding: [0xc3]
258258
entry:
259259
%t= load i8, ptr %a
@@ -264,12 +264,12 @@ entry:
264264
define i16 @and16mr(ptr %a, i16 noundef %b) {
265265
; CHECK-LABEL: and16mr:
266266
; CHECK: # %bb.0: # %entry
267-
; CHECK-NEXT: andw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x21,0x37]
267+
; CHECK-NEXT: andw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x23,0x37]
268268
; CHECK-NEXT: retq # encoding: [0xc3]
269269
;
270270
; NF-LABEL: and16mr:
271271
; NF: # %bb.0: # %entry
272-
; NF-NEXT: {nf} andw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x21,0x37]
272+
; NF-NEXT: {nf} andw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x23,0x37]
273273
; NF-NEXT: retq # encoding: [0xc3]
274274
entry:
275275
%t= load i16, ptr %a
@@ -280,12 +280,12 @@ entry:
280280
define i32 @and32mr(ptr %a, i32 noundef %b) {
281281
; CHECK-LABEL: and32mr:
282282
; CHECK: # %bb.0: # %entry
283-
; CHECK-NEXT: andl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x21,0x37]
283+
; CHECK-NEXT: andl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x23,0x37]
284284
; CHECK-NEXT: retq # encoding: [0xc3]
285285
;
286286
; NF-LABEL: and32mr:
287287
; NF: # %bb.0: # %entry
288-
; NF-NEXT: {nf} andl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x21,0x37]
288+
; NF-NEXT: {nf} andl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x23,0x37]
289289
; NF-NEXT: retq # encoding: [0xc3]
290290
entry:
291291
%t= load i32, ptr %a
@@ -296,12 +296,12 @@ entry:
296296
define i64 @and64mr(ptr %a, i64 noundef %b) {
297297
; CHECK-LABEL: and64mr:
298298
; CHECK: # %bb.0: # %entry
299-
; CHECK-NEXT: andq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x21,0x37]
299+
; CHECK-NEXT: andq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x23,0x37]
300300
; CHECK-NEXT: retq # encoding: [0xc3]
301301
;
302302
; NF-LABEL: and64mr:
303303
; NF: # %bb.0: # %entry
304-
; NF-NEXT: {nf} andq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x21,0x37]
304+
; NF-NEXT: {nf} andq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x23,0x37]
305305
; NF-NEXT: retq # encoding: [0xc3]
306306
entry:
307307
%t= load i64, ptr %a

‎llvm/test/CodeGen/X86/apx/or.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -248,12 +248,12 @@ entry:
248248
define i8 @or8mr(ptr %a, i8 noundef %b) {
249249
; CHECK-LABEL: or8mr:
250250
; CHECK: # %bb.0: # %entry
251-
; CHECK-NEXT: orb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x08,0x37]
251+
; CHECK-NEXT: orb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x0a,0x37]
252252
; CHECK-NEXT: retq # encoding: [0xc3]
253253
;
254254
; NF-LABEL: or8mr:
255255
; NF: # %bb.0: # %entry
256-
; NF-NEXT: {nf} orb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x08,0x37]
256+
; NF-NEXT: {nf} orb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x0a,0x37]
257257
; NF-NEXT: retq # encoding: [0xc3]
258258
entry:
259259
%t= load i8, ptr %a
@@ -264,12 +264,12 @@ entry:
264264
define i16 @or16mr(ptr %a, i16 noundef %b) {
265265
; CHECK-LABEL: or16mr:
266266
; CHECK: # %bb.0: # %entry
267-
; CHECK-NEXT: orw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x09,0x37]
267+
; CHECK-NEXT: orw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x0b,0x37]
268268
; CHECK-NEXT: retq # encoding: [0xc3]
269269
;
270270
; NF-LABEL: or16mr:
271271
; NF: # %bb.0: # %entry
272-
; NF-NEXT: {nf} orw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x09,0x37]
272+
; NF-NEXT: {nf} orw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x0b,0x37]
273273
; NF-NEXT: retq # encoding: [0xc3]
274274
entry:
275275
%t= load i16, ptr %a
@@ -280,12 +280,12 @@ entry:
280280
define i32 @or32mr(ptr %a, i32 noundef %b) {
281281
; CHECK-LABEL: or32mr:
282282
; CHECK: # %bb.0: # %entry
283-
; CHECK-NEXT: orl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x09,0x37]
283+
; CHECK-NEXT: orl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x0b,0x37]
284284
; CHECK-NEXT: retq # encoding: [0xc3]
285285
;
286286
; NF-LABEL: or32mr:
287287
; NF: # %bb.0: # %entry
288-
; NF-NEXT: {nf} orl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x09,0x37]
288+
; NF-NEXT: {nf} orl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x0b,0x37]
289289
; NF-NEXT: retq # encoding: [0xc3]
290290
entry:
291291
%t= load i32, ptr %a
@@ -296,12 +296,12 @@ entry:
296296
define i64 @or64mr(ptr %a, i64 noundef %b) {
297297
; CHECK-LABEL: or64mr:
298298
; CHECK: # %bb.0: # %entry
299-
; CHECK-NEXT: orq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x09,0x37]
299+
; CHECK-NEXT: orq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x0b,0x37]
300300
; CHECK-NEXT: retq # encoding: [0xc3]
301301
;
302302
; NF-LABEL: or64mr:
303303
; NF: # %bb.0: # %entry
304-
; NF-NEXT: {nf} orq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x09,0x37]
304+
; NF-NEXT: {nf} orq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x0b,0x37]
305305
; NF-NEXT: retq # encoding: [0xc3]
306306
entry:
307307
%t= load i64, ptr %a

‎llvm/test/CodeGen/X86/apx/xor.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -248,12 +248,12 @@ entry:
248248
define i8 @xor8mr(ptr %a, i8 noundef %b) {
249249
; CHECK-LABEL: xor8mr:
250250
; CHECK: # %bb.0: # %entry
251-
; CHECK-NEXT: xorb %sil, (%rdi), %al # encoding: [0x62,0xf4,0x7c,0x18,0x30,0x37]
251+
; CHECK-NEXT: xorb (%rdi), %sil, %al # encoding: [0x62,0xf4,0x7c,0x18,0x32,0x37]
252252
; CHECK-NEXT: retq # encoding: [0xc3]
253253
;
254254
; NF-LABEL: xor8mr:
255255
; NF: # %bb.0: # %entry
256-
; NF-NEXT: {nf} xorb %sil, (%rdi), %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x30,0x37]
256+
; NF-NEXT: {nf} xorb (%rdi), %sil, %al # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x32,0x37]
257257
; NF-NEXT: retq # encoding: [0xc3]
258258
entry:
259259
%t= load i8, ptr %a
@@ -264,12 +264,12 @@ entry:
264264
define i16 @xor16mr(ptr %a, i16 noundef %b) {
265265
; CHECK-LABEL: xor16mr:
266266
; CHECK: # %bb.0: # %entry
267-
; CHECK-NEXT: xorw %si, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x31,0x37]
267+
; CHECK-NEXT: xorw (%rdi), %si, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x33,0x37]
268268
; CHECK-NEXT: retq # encoding: [0xc3]
269269
;
270270
; NF-LABEL: xor16mr:
271271
; NF: # %bb.0: # %entry
272-
; NF-NEXT: {nf} xorw %si, (%rdi), %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x31,0x37]
272+
; NF-NEXT: {nf} xorw (%rdi), %si, %ax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7d,0x1c,0x33,0x37]
273273
; NF-NEXT: retq # encoding: [0xc3]
274274
entry:
275275
%t= load i16, ptr %a
@@ -280,12 +280,12 @@ entry:
280280
define i32 @xor32mr(ptr %a, i32 noundef %b) {
281281
; CHECK-LABEL: xor32mr:
282282
; CHECK: # %bb.0: # %entry
283-
; CHECK-NEXT: xorl %esi, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x31,0x37]
283+
; CHECK-NEXT: xorl (%rdi), %esi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x33,0x37]
284284
; CHECK-NEXT: retq # encoding: [0xc3]
285285
;
286286
; NF-LABEL: xor32mr:
287287
; NF: # %bb.0: # %entry
288-
; NF-NEXT: {nf} xorl %esi, (%rdi), %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x31,0x37]
288+
; NF-NEXT: {nf} xorl (%rdi), %esi, %eax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0x7c,0x1c,0x33,0x37]
289289
; NF-NEXT: retq # encoding: [0xc3]
290290
entry:
291291
%t= load i32, ptr %a
@@ -296,12 +296,12 @@ entry:
296296
define i64 @xor64mr(ptr %a, i64 noundef %b) {
297297
; CHECK-LABEL: xor64mr:
298298
; CHECK: # %bb.0: # %entry
299-
; CHECK-NEXT: xorq %rsi, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x31,0x37]
299+
; CHECK-NEXT: xorq (%rdi), %rsi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x33,0x37]
300300
; CHECK-NEXT: retq # encoding: [0xc3]
301301
;
302302
; NF-LABEL: xor64mr:
303303
; NF: # %bb.0: # %entry
304-
; NF-NEXT: {nf} xorq %rsi, (%rdi), %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x31,0x37]
304+
; NF-NEXT: {nf} xorq (%rdi), %rsi, %rax # EVEX TO EVEX Compression encoding: [0x62,0xf4,0xfc,0x1c,0x33,0x37]
305305
; NF-NEXT: retq # encoding: [0xc3]
306306
entry:
307307
%t= load i64, ptr %a

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