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[RISCV] Support VP_SPLAT mask operations (#132345)
When val is a constant, it will: (vp.splat val, mask, vl) -> (select val, (riscv_vmset_vl vl), (riscv_vmclr_vl vl)) Otherwise: (vp.splat val, mask, vl) -> (vmsne_vl (vmv_v_x_vl (zext val), vl), splat(zero), mask, vl) --------- Co-authored-by: yanming <[email protected]>
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 21 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -810,6 +810,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::EXPERIMENTAL_VP_SPLICE, VT, Custom);
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setOperationAction(ISD::EXPERIMENTAL_VP_REVERSE, VT, Custom);
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setOperationAction(ISD::EXPERIMENTAL_VP_SPLAT, VT, Custom);
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setOperationPromotedToType(
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ISD::VECTOR_SPLICE, VT,
@@ -12786,8 +12787,26 @@ SDValue RISCVTargetLowering::lowerVPSplatExperimental(SDValue Op,
1278612787
Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
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}
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12789-
SDValue Result =
12790-
lowerScalarSplat(SDValue(), Val, VL, ContainerVT, DL, DAG, Subtarget);
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SDValue Result;
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if (VT.getScalarType() == MVT::i1) {
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if (auto *C = dyn_cast<ConstantSDNode>(Val)) {
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Result =
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DAG.getNode(C->isZero() ? RISCVISD::VMCLR_VL : RISCVISD::VMSET_VL, DL,
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ContainerVT, VL);
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} else {
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MVT WidenVT = ContainerVT.changeVectorElementType(MVT::i8);
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SDValue LHS =
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DAG.getNode(RISCVISD::VMV_V_X_VL, DL, WidenVT, DAG.getUNDEF(WidenVT),
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DAG.getZExtOrTrunc(Val, DL, Subtarget.getXLenVT()), VL);
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SDValue RHS = DAG.getConstant(0, DL, WidenVT);
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Result = DAG.getNode(RISCVISD::SETCC_VL, DL, ContainerVT,
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{LHS, RHS, DAG.getCondCode(ISD::SETNE),
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DAG.getUNDEF(ContainerVT), Mask, VL});
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}
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} else {
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Result =
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lowerScalarSplat(SDValue(), Val, VL, ContainerVT, DL, DAG, Subtarget);
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}
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if (!VT.isFixedLengthVector())
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return Result;

‎llvm/test/CodeGen/RISCV/rvv/vp-splat-mask.ll

Lines changed: 107 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,107 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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define <vscale x 1 x i1> @vp_splat_nxv1i1_true_unmasked(i32 zeroext %evl) {
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; CHECK-LABEL: vp_splat_nxv1i1_true_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vmset.m v0
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; CHECK-NEXT: ret
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%splat = call <vscale x 1 x i1> @llvm.experimental.vp.splat.nxv1i1(i1 true, <vscale x 1 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 1 x i1> %splat
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}
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define <vscale x 1 x i1> @vp_splat_nxv1i1_false_unmasked(i32 zeroext %evl) {
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; CHECK-LABEL: vp_splat_nxv1i1_false_unmasked:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
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; CHECK-NEXT: vmclr.m v0
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; CHECK-NEXT: ret
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%splat = call <vscale x 1 x i1> @llvm.experimental.vp.splat.nxv1i1(i1 false, <vscale x 1 x i1> splat (i1 true), i32 %evl)
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ret <vscale x 1 x i1> %splat
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}
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define <vscale x 1 x i1> @vp_splat_nxv1i1(i1 %val, <vscale x 1 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_splat_nxv1i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
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; CHECK-NEXT: ret
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%splat = call <vscale x 1 x i1> @llvm.experimental.vp.splat.nxv1i1(i1 %val, <vscale x 1 x i1> %m, i32 %evl)
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ret <vscale x 1 x i1> %splat
34+
}
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36+
define <vscale x 2 x i1> @vp_splat_nxv2i1(i1 %val, <vscale x 2 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_splat_nxv2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
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; CHECK-NEXT: ret
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%splat = call <vscale x 2 x i1> @llvm.experimental.vp.splat.nxv2i1(i1 %val, <vscale x 2 x i1> %m, i32 %evl)
44+
ret <vscale x 2 x i1> %splat
45+
}
46+
47+
define <vscale x 4 x i1> @vp_splat_nxv4i1(i1 %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
48+
; CHECK-LABEL: vp_splat_nxv4i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
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; CHECK-NEXT: ret
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%splat = call <vscale x 4 x i1> @llvm.experimental.vp.splat.nxv4i1(i1 %val, <vscale x 4 x i1> %m, i32 %evl)
55+
ret <vscale x 4 x i1> %splat
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}
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58+
define <vscale x 8 x i1> @vp_splat_nxv8i1(i1 %val, <vscale x 8 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vp_splat_nxv8i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
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; CHECK-NEXT: vmv.v.x v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
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; CHECK-NEXT: ret
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%splat = call <vscale x 8 x i1> @llvm.experimental.vp.splat.nxv8i1(i1 %val, <vscale x 8 x i1> %m, i32 %evl)
66+
ret <vscale x 8 x i1> %splat
67+
}
68+
69+
define <vscale x 16 x i1> @vp_splat_nxv16i1(i1 %val, <vscale x 16 x i1> %m, i32 zeroext %evl) {
70+
; CHECK-LABEL: vp_splat_nxv16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.x v10, a0
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; CHECK-NEXT: vmsne.vi v8, v10, 0, v0.t
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: ret
77+
%splat = call <vscale x 16 x i1> @llvm.experimental.vp.splat.nxv16i1(i1 %val, <vscale x 16 x i1> %m, i32 %evl)
78+
ret <vscale x 16 x i1> %splat
79+
}
80+
81+
define <vscale x 32 x i1> @vp_splat_nxv32i1(i1 %val, <vscale x 32 x i1> %m, i32 zeroext %evl) {
82+
; CHECK-LABEL: vp_splat_nxv32i1:
83+
; CHECK: # %bb.0:
84+
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
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; CHECK-NEXT: vmv.v.x v12, a0
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; CHECK-NEXT: vmsne.vi v8, v12, 0, v0.t
87+
; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: ret
89+
%splat = call <vscale x 32 x i1> @llvm.experimental.vp.splat.nxv32i1(i1 %val, <vscale x 32 x i1> %m, i32 %evl)
90+
ret <vscale x 32 x i1> %splat
91+
}
92+
93+
define <vscale x 64 x i1> @vp_splat_nxv64i1(i1 %val, <vscale x 64 x i1> %m, i32 zeroext %evl) {
94+
; CHECK-LABEL: vp_splat_nxv64i1:
95+
; CHECK: # %bb.0:
96+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
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; CHECK-NEXT: vmv.v.x v16, a0
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; CHECK-NEXT: vmsne.vi v8, v16, 0, v0.t
99+
; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: ret
101+
%splat = call <vscale x 64 x i1> @llvm.experimental.vp.splat.nxv64i1(i1 %val, <vscale x 64 x i1> %m, i32 %evl)
102+
ret <vscale x 64 x i1> %splat
103+
}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32: {{.*}}
107+
; RV64: {{.*}}

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