Skip to content

Commit b7662b1

Browse files
JonPsson1JonPsson1
committed
Remove mapping, and remove MIs during PEI.
1 parent 12ae89c commit b7662b1

12 files changed

+49
-41
lines changed

‎llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp

Lines changed: 14 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -66,22 +66,6 @@ SystemZFrameLowering::create(const SystemZSubtarget &STI) {
6666
return std::make_unique<SystemZELFFrameLowering>();
6767
}
6868

69-
MachineBasicBlock::iterator SystemZFrameLowering::eliminateCallFramePseudoInstr(
70-
MachineFunction &MF, MachineBasicBlock &MBB,
71-
MachineBasicBlock::iterator MI) const {
72-
switch (MI->getOpcode()) {
73-
case SystemZ::ADJCALLSTACKDOWN:
74-
case SystemZ::ADJCALLSTACKUP:
75-
assert(hasReservedCallFrame(MF) &&
76-
"ADJSTACKDOWN and ADJSTACKUP should be no-ops");
77-
return MBB.erase(MI);
78-
break;
79-
80-
default:
81-
llvm_unreachable("Unexpected call frame instruction");
82-
}
83-
}
84-
8569
namespace {
8670
struct SZFrameSortingObj {
8771
bool IsValid = false; // True if we care about this Object.
@@ -439,6 +423,16 @@ bool SystemZELFFrameLowering::restoreCalleeSavedRegisters(
439423
return true;
440424
}
441425

426+
static void removeCallSeqPseudos(MachineFunction &MF) {
427+
// TODO: These could have been removed in finalize isel already as they are
428+
// not mapped as frame instructions. See comment in emitAdjCallStack().
429+
for (auto &MBB : MF)
430+
for (MachineInstr &MI : llvm::make_early_inc_range(MBB))
431+
if (MI.getOpcode() == SystemZ::ADJCALLSTACKDOWN ||
432+
MI.getOpcode() == SystemZ::ADJCALLSTACKUP)
433+
MI.eraseFromParent();
434+
}
435+
442436
void SystemZELFFrameLowering::processFunctionBeforeFrameFinalized(
443437
MachineFunction &MF, RegScavenger *RS) const {
444438
MachineFrameInfo &MFFrame = MF.getFrameInfo();
@@ -480,6 +474,8 @@ void SystemZELFFrameLowering::processFunctionBeforeFrameFinalized(
480474
ZFI->getRestoreGPRRegs().LowGPR != SystemZ::R6D)
481475
for (auto &MO : MRI->use_nodbg_operands(SystemZ::R6D))
482476
MO.setIsKill(false);
477+
478+
removeCallSeqPseudos(MF);
483479
}
484480

485481
// Emit instructions before MBBI (in MBB) to add NumBytes to Reg.
@@ -1467,6 +1463,8 @@ void SystemZXPLINKFrameLowering::processFunctionBeforeFrameFinalized(
14671463
// with existing compilers.
14681464
MFFrame.setMaxCallFrameSize(
14691465
std::max(64U, (unsigned)alignTo(MFFrame.getMaxCallFrameSize(), 64)));
1466+
1467+
removeCallSeqPseudos(MF);
14701468
}
14711469

14721470
// Determines the size of the frame, and creates the deferred spill objects.

‎llvm/lib/Target/SystemZ/SystemZFrameLowering.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -41,9 +41,6 @@ class SystemZFrameLowering : public TargetFrameLowering {
4141
}
4242

4343
bool hasReservedCallFrame(const MachineFunction &MF) const override;
44-
MachineBasicBlock::iterator
45-
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
46-
MachineBasicBlock::iterator MI) const override;
4744
};
4845

4946
class SystemZELFFrameLowering : public SystemZFrameLowering {

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8105,20 +8105,22 @@ static void createPHIsForSelects(SmallVector<MachineInstr*, 8> &Selects,
81058105
MachineBasicBlock *
81068106
SystemZTargetLowering::emitAdjCallStack(MachineInstr &MI,
81078107
MachineBasicBlock *BB) const {
8108+
MachineFunction &MF = *BB->getParent();
8109+
MachineFrameInfo &MFI = MF.getFrameInfo();
8110+
auto *TFL = Subtarget.getFrameLowering<SystemZFrameLowering>();
8111+
assert(TFL->hasReservedCallFrame(MF) &&
8112+
"ADJSTACKDOWN and ADJSTACKUP should be no-ops");
81088113
// Do the work of MachineFrameInfo::computeMaxCallFrameSize() early and
81098114
// remove these nodes. Given that these nodes start out as a glued sequence
81108115
// it seems best to handle them here after instruction selection and
81118116
// scheduling.
8112-
MachineFrameInfo &MFI = BB->getParent()->getFrameInfo();
81138117
uint32_t NumBytes = MI.getOperand(0).getImm();
81148118
if (NumBytes > MFI.getMaxCallFrameSize())
81158119
MFI.setMaxCallFrameSize(NumBytes);
81168120
MFI.setAdjustsStack(true);
81178121

8118-
// Set the NumBytes value to 0 to avoid problems of maintaining the call
8119-
// frame size across CFG edges. TODO: MI could be erased, but it seems to
8120-
// help scheduling around calls slightly (fix MachineScheduler + handle the
8121-
// adjustsStack implication).
8122+
// TODO: MI should be erased. For now, keep it around as it seems to help
8123+
// eliminate COPYs around calls slightly in general (fix MachineScheduler?).
81228124
MI.getOperand(0).setImm(0);
81238125

81248126
return BB;

‎llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ static uint64_t allOnes(unsigned int Count) {
5959
void SystemZInstrInfo::anchor() {}
6060

6161
SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
62-
: SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
62+
: SystemZGenInstrInfo(-1, -1),
6363
RI(sti.getSpecialRegisters()->getReturnFunctionAddressRegister()),
6464
STI(sti) {}
6565

‎llvm/test/CodeGen/SystemZ/call-zos-vararg.ll

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -88,16 +88,13 @@ entry:
8888
ret i64 %retval
8989
}
9090

91-
; TODO: Unfortunately the lgdr is scheduled below the COPY from $r1d, causing
92-
; an overlap and thus an extra copy.
9391
; CHECK-LABEL: call_vararg_both0:
9492
; CHECK: stmg 6, 7, 1872(4)
9593
; CHECK-NEXT: aghi 4, -192
9694
; CHECK-NEXT: lg 6, 40(5)
9795
; CHECK-NEXT: lg 5, 32(5)
98-
; CHECK-NEXT: lgdr 0, 0
9996
; CHECK-NEXT: lgr 2, 1
100-
; CHECK-NEXT: lgr 1, 0
97+
; CHECK-NEXT: lgdr 1, 0
10198
; CHECK-NEXT: basr 7, 6
10299
; CHECK-NEXT: bcr 0, 0
103100
; CHECK-NEXT: lg 7, 2072(4)

‎llvm/test/CodeGen/SystemZ/cond-move-04.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,10 +64,12 @@ body: |
6464
CHIMux %3, 0, implicit-def $cc
6565
%0 = LOCRMux undef %0, %5, 14, 6, implicit $cc
6666
%0 = LOCRMux %0, %2, 14, 6, implicit killed $cc
67+
ADJCALLSTACKDOWN 0, 0
6768
%7 = LGFR %0
6869
$r3d = LGHI 0
6970
$r4d = COPY %7
7071
CallBRASL @foo, undef $r2d, killed $r3d, killed $r4d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def dead $r2d
72+
ADJCALLSTACKUP 0, 0
7173
J %bb.1
7274
7375
...

‎llvm/test/CodeGen/SystemZ/cond-move-08.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,9 @@ body: |
154154
J %bb.4
155155
156156
bb.4.bb33:
157+
ADJCALLSTACKDOWN 0, 0
157158
CallBRASL @fun, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
159+
ADJCALLSTACKUP 0, 0
158160
STRL %4, @globvar :: (store (s32) into @globvar)
159161
CLFIMux undef %23:grx32bit, 1, implicit-def $cc
160162
%25:grx32bit = LHIMux 0

‎llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,9 +44,11 @@ body: |
4444
%11:gr32bit = SELRMux %8, %9:grx32bit, 14, 6, implicit killed $cc
4545
CHIMux %6, 2, implicit-def $cc
4646
%0:gr32bit = SELRMux %11, %5, 14, 8, implicit killed $cc
47+
ADJCALLSTACKDOWN 0, 0
4748
%10:gr64bit = LGFR %0
4849
$r2d = COPY %10
4950
CallBRASL @foo, killed $r2d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc
51+
ADJCALLSTACKUP 0, 0
5052
J %bb.1
5153
5254
...

‎llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -199,12 +199,18 @@ body: |
199199
200200
%32:gr64bit = COPY $r3d
201201
%0:gr64bit = COPY $r2d
202+
ADJCALLSTACKDOWN 0, 0
202203
CallBRASL @sre_malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d
203204
%1:addr64bit = COPY $r2d
205+
ADJCALLSTACKUP 0, 0
206+
ADJCALLSTACKDOWN 0, 0
204207
CallBRASL @sre_malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d
205208
%2:addr64bit = COPY $r2d
209+
ADJCALLSTACKUP 0, 0
206210
%3:gr32bit = AHIMuxK %0.subreg_l32, -1, implicit-def dead $cc
211+
ADJCALLSTACKDOWN 0, 0
207212
CallBRASL @malloc, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc
213+
ADJCALLSTACKUP 0, 0
208214
%55:gr32bit = AHIMuxK %0.subreg_l32, 3, implicit-def dead $cc
209215
%56:addr64bit = LGHI 0
210216
%57:gr64bit = COPY %0

‎llvm/test/CodeGen/SystemZ/frame-28.mir

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,9 @@ body: |
177177
VST64 renamable $f16d, %stack.0, 0, $noreg
178178
VST64 renamable $f16d, %stack.0, 0, $noreg
179179
VST64 renamable $f16d, %stack.1, 0, $noreg
180+
ADJCALLSTACKDOWN 0, 0
180181
CallBRASL @foo, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc, implicit-def $r2l
182+
ADJCALLSTACKUP 0, 0
181183
$f17d = IMPLICIT_DEF
182184
VST64 renamable $f17d, %stack.1, 0, $noreg
183185
Return

‎llvm/test/CodeGen/SystemZ/swifterror.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -30,8 +30,8 @@ entry:
3030
define float @caller(ptr %error_ref) {
3131
; CHECK-LABEL: caller:
3232
; Make a copy of error_ref because r2 is getting clobbered
33-
; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2
34-
; CHECK-DAG: lghi %r9, 0
33+
; CHECK: lgr %r[[REG1:[0-9]+]], %r2
34+
; CHECK: lghi %r9, 0
3535
; CHECK: brasl %r14, foo
3636
; CHECK: %r2, %r9
3737
; CHECK: jlh
@@ -197,7 +197,7 @@ define void @foo_sret(ptr sret(%struct.S) %agg.result, i32 %val1, ptr swifterror
197197
; CHECK-LABEL: foo_sret:
198198
; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2
199199
; CHECK-DAG: lr %r[[REG2:[0-9]+]], %r3
200-
; CHECK-DAG: lghi %r2, 16
200+
; CHECK: lghi %r2, 16
201201
; CHECK: brasl %r14, malloc
202202
; CHECK: mvi 8(%r2), 1
203203
; CHECK: st %r[[REG2]], 4(%r[[REG1]])
@@ -280,7 +280,7 @@ define float @caller_with_multiple_swifterror_values(ptr %error_ref, ptr %error_
280280
; CHECK-DAG: lgr %r[[REG1:[0-9]+]], %r2
281281
; CHECK-DAG: lgr %r[[REG2:[0-9]+]], %r3
282282
; The first swifterror value:
283-
; CHECK-DAG: lghi %r9, 0
283+
; CHECK: lghi %r9, 0
284284
; CHECK: brasl %r14, foo
285285
; CHECK: ltgr %r2, %r9
286286
; CHECK: jlh

‎llvm/test/CodeGen/SystemZ/vector-constrained-fp-intrinsics.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1649,8 +1649,8 @@ define <2 x double> @constrained_vector_powi_v2f64() #0 {
16491649
; S390X-NEXT: brasl %r14, __powidf2@PLT
16501650
; S390X-NEXT: larl %r1, .LCPI36_1
16511651
; S390X-NEXT: ld %f1, 0(%r1)
1652-
; S390X-NEXT: lghi %r2, 3
16531652
; S390X-NEXT: ldr %f8, %f0
1653+
; S390X-NEXT: lghi %r2, 3
16541654
; S390X-NEXT: ldr %f0, %f1
16551655
; S390X-NEXT: brasl %r14, __powidf2@PLT
16561656
; S390X-NEXT: ldr %f2, %f8
@@ -1707,14 +1707,14 @@ define <3 x float> @constrained_vector_powi_v3f32() #0 {
17071707
; S390X-NEXT: brasl %r14, __powisf2@PLT
17081708
; S390X-NEXT: larl %r1, .LCPI37_1
17091709
; S390X-NEXT: le %f1, 0(%r1)
1710-
; S390X-NEXT: lghi %r2, 3
17111710
; S390X-NEXT: ler %f8, %f0
1711+
; S390X-NEXT: lghi %r2, 3
17121712
; S390X-NEXT: ler %f0, %f1
17131713
; S390X-NEXT: brasl %r14, __powisf2@PLT
17141714
; S390X-NEXT: larl %r1, .LCPI37_2
17151715
; S390X-NEXT: le %f1, 0(%r1)
1716-
; S390X-NEXT: lghi %r2, 3
17171716
; S390X-NEXT: ler %f9, %f0
1717+
; S390X-NEXT: lghi %r2, 3
17181718
; S390X-NEXT: ler %f0, %f1
17191719
; S390X-NEXT: brasl %r14, __powisf2@PLT
17201720
; S390X-NEXT: ler %f2, %f9
@@ -1784,14 +1784,14 @@ define void @constrained_vector_powi_v3f64(ptr %a) #0 {
17841784
; S390X-NEXT: brasl %r14, __powidf2@PLT
17851785
; S390X-NEXT: larl %r1, .LCPI38_1
17861786
; S390X-NEXT: ld %f1, 0(%r1)
1787-
; S390X-NEXT: lghi %r2, 3
17881787
; S390X-NEXT: ldr %f8, %f0
1788+
; S390X-NEXT: lghi %r2, 3
17891789
; S390X-NEXT: ldr %f0, %f1
17901790
; S390X-NEXT: brasl %r14, __powidf2@PLT
17911791
; S390X-NEXT: larl %r1, .LCPI38_2
17921792
; S390X-NEXT: ld %f1, 0(%r1)
1793-
; S390X-NEXT: lghi %r2, 3
17941793
; S390X-NEXT: ldr %f9, %f0
1794+
; S390X-NEXT: lghi %r2, 3
17951795
; S390X-NEXT: ldr %f0, %f1
17961796
; S390X-NEXT: brasl %r14, __powidf2@PLT
17971797
; S390X-NEXT: std %f0, 16(%r13)
@@ -1865,20 +1865,20 @@ define <4 x double> @constrained_vector_powi_v4f64() #0 {
18651865
; S390X-NEXT: brasl %r14, __powidf2@PLT
18661866
; S390X-NEXT: larl %r1, .LCPI39_1
18671867
; S390X-NEXT: ld %f1, 0(%r1)
1868-
; S390X-NEXT: lghi %r2, 3
18691868
; S390X-NEXT: ldr %f8, %f0
1869+
; S390X-NEXT: lghi %r2, 3
18701870
; S390X-NEXT: ldr %f0, %f1
18711871
; S390X-NEXT: brasl %r14, __powidf2@PLT
18721872
; S390X-NEXT: larl %r1, .LCPI39_2
18731873
; S390X-NEXT: ld %f1, 0(%r1)
1874-
; S390X-NEXT: lghi %r2, 3
18751874
; S390X-NEXT: ldr %f9, %f0
1875+
; S390X-NEXT: lghi %r2, 3
18761876
; S390X-NEXT: ldr %f0, %f1
18771877
; S390X-NEXT: brasl %r14, __powidf2@PLT
18781878
; S390X-NEXT: larl %r1, .LCPI39_3
18791879
; S390X-NEXT: ld %f1, 0(%r1)
1880-
; S390X-NEXT: lghi %r2, 3
18811880
; S390X-NEXT: ldr %f10, %f0
1881+
; S390X-NEXT: lghi %r2, 3
18821882
; S390X-NEXT: ldr %f0, %f1
18831883
; S390X-NEXT: brasl %r14, __powidf2@PLT
18841884
; S390X-NEXT: ldr %f2, %f10

0 commit comments

Comments
 (0)