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[AMDGPU][GlobalISel] Make selectVOP3PMadMixModsImpl same as the SelectionDAG counterpart
The current `selectVOP3PMadMixModsImpl` can produce `V_MAD_FIX_F32` instruction that violates constant bus restriction, while its `SelectionDAG` counterpart doesn't. The culprit is in the copy stripping while the SelectionDAG version only has a bitcast stripping. This PR simply aligns the two version.
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4 files changed

+70
-22
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 5 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5312,26 +5312,20 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
53125312
// Only change Src if src modifier could be gained. In such cases new Src
53135313
// could be sgpr but this does not violate constant bus restriction for
53145314
// instruction that is being selected.
5315-
// Note: Src is not changed when there is only a simple sgpr to vgpr copy
5316-
// since this could violate constant bus restriction.
5317-
Register PeekSrc = stripCopy(Src, *MRI);
5315+
Src = stripBitCast(Src, *MRI);
53185316

53195317
const auto CheckAbsNeg = [&]() {
53205318
// Be careful about folding modifiers if we already have an abs. fneg is
53215319
// applied last, so we don't want to apply an earlier fneg.
53225320
if ((Mods & SISrcMods::ABS) == 0) {
53235321
unsigned ModsTmp;
5324-
std::tie(PeekSrc, ModsTmp) = selectVOP3ModsImpl(PeekSrc);
5322+
std::tie(Src, ModsTmp) = selectVOP3ModsImpl(Src);
53255323

5326-
if ((ModsTmp & SISrcMods::NEG) != 0) {
5324+
if ((ModsTmp & SISrcMods::NEG) != 0)
53275325
Mods ^= SISrcMods::NEG;
5328-
Src = PeekSrc;
5329-
}
53305326

5331-
if ((ModsTmp & SISrcMods::ABS) != 0) {
5327+
if ((ModsTmp & SISrcMods::ABS) != 0)
53325328
Mods |= SISrcMods::ABS;
5333-
Src = PeekSrc;
5334-
}
53355329
}
53365330
};
53375331

@@ -5344,8 +5338,7 @@ AMDGPUInstructionSelector::selectVOP3PMadMixModsImpl(MachineOperand &Root,
53445338

53455339
Mods |= SISrcMods::OP_SEL_1;
53465340

5347-
if (isExtractHiElt(*MRI, PeekSrc, PeekSrc)) {
5348-
Src = PeekSrc;
5341+
if (isExtractHiElt(*MRI, Src, Src)) {
53495342
Mods |= SISrcMods::OP_SEL_0;
53505343
CheckAbsNeg();
53515344
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -73,10 +73,14 @@ define amdgpu_vs <5 x float> @test_5xf16_5xf32_add_ext_mul(<5 x half> inreg %x,
7373
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v2, s8
7474
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s9
7575
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s10
76+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s11, s0, 16
77+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s12, s1, 16
78+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s13, s3, 16
79+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s14, s4, 16
7680
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v0, s0, s3, v0 op_sel_hi:[1,1,0]
77-
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v1, s0, s3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
81+
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v1, s11, s13, v1 op_sel_hi:[1,1,0]
7882
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v2, s1, s4, v2 op_sel_hi:[1,1,0]
79-
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v3, s1, s4, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
83+
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v3, s12, s14, v3 op_sel_hi:[1,1,0]
8084
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v4, s2, s5, v4 op_sel_hi:[1,1,0]
8185
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
8286
.entry:
@@ -117,12 +121,18 @@ define amdgpu_vs <6 x float> @test_6xf16_6xf32_add_ext_mul_rhs(<6 x half> inreg
117121
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v3, s9
118122
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v4, s10
119123
; GFX10-FAST-DENORM-NEXT: v_mov_b32_e32 v5, s11
124+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s12, s0, 16
125+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s13, s1, 16
126+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s6, s2, 16
127+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s14, s3, 16
128+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s15, s4, 16
129+
; GFX10-FAST-DENORM-NEXT: s_lshr_b32 s16, s5, 16
120130
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v0, s0, s3, v0 op_sel_hi:[1,1,0]
121-
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v1, s0, s3, v1 op_sel:[1,1,0] op_sel_hi:[1,1,0]
131+
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v1, s12, s14, v1 op_sel_hi:[1,1,0]
122132
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v2, s1, s4, v2 op_sel_hi:[1,1,0]
123-
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v3, s1, s4, v3 op_sel:[1,1,0] op_sel_hi:[1,1,0]
133+
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v3, s13, s15, v3 op_sel_hi:[1,1,0]
124134
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v4, s2, s5, v4 op_sel_hi:[1,1,0]
125-
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v5, s2, s5, v5 op_sel:[1,1,0] op_sel_hi:[1,1,0]
135+
; GFX10-FAST-DENORM-NEXT: v_fma_mix_f32 v5, s6, s16, v5 op_sel_hi:[1,1,0]
126136
; GFX10-FAST-DENORM-NEXT: ; return to shader part epilog
127137
.entry:
128138
%a = fmul fast <6 x half> %x, %y

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2555,9 +2555,9 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) {
25552555
; GFX9-FLUSH-NEXT: v_rcp_f32_e32 v1, v1
25562556
; GFX9-FLUSH-NEXT: v_mad_mixlo_f16 v0, s0, v0, 0 op_sel_hi:[1,0,0]
25572557
; GFX9-FLUSH-NEXT: v_div_fixup_f16 v0, v0, v2, s0
2558-
; GFX9-FLUSH-NEXT: v_mad_mixlo_f16 v1, s0, v1, 0 op_sel:[1,0,0] op_sel_hi:[1,0,0]
2559-
; GFX9-FLUSH-NEXT: v_mov_b32_e32 v2, s3
2560-
; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v1, s2, v2
2558+
; GFX9-FLUSH-NEXT: v_mov_b32_e32 v2, s2
2559+
; GFX9-FLUSH-NEXT: v_mad_mixlo_f16 v1, s3, v1, 0 op_sel_hi:[1,0,0]
2560+
; GFX9-FLUSH-NEXT: v_div_fixup_f16 v1, v1, v2, s3
25612561
; GFX9-FLUSH-NEXT: v_pack_b32_f16 v0, v0, v1
25622562
; GFX9-FLUSH-NEXT: v_readfirstlane_b32 s0, v0
25632563
; GFX9-FLUSH-NEXT: ; return to shader part epilog
@@ -2571,7 +2571,7 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) {
25712571
; GFX10-NEXT: v_rcp_f32_e32 v0, v0
25722572
; GFX10-NEXT: v_rcp_f32_e32 v1, v1
25732573
; GFX10-NEXT: v_fma_mixlo_f16 v0, s0, v0, 0 op_sel_hi:[1,0,0]
2574-
; GFX10-NEXT: v_fma_mixlo_f16 v1, s0, v1, 0 op_sel:[1,0,0] op_sel_hi:[1,0,0]
2574+
; GFX10-NEXT: v_fma_mixlo_f16 v1, s3, v1, 0 op_sel_hi:[1,0,0]
25752575
; GFX10-NEXT: v_div_fixup_f16 v0, v0, s1, s0
25762576
; GFX10-NEXT: v_div_fixup_f16 v1, v1, s2, s3
25772577
; GFX10-NEXT: v_pack_b32_f16 v0, v0, v1
@@ -2588,7 +2588,7 @@ define amdgpu_ps i32 @s_fdiv_v2f16(i32 inreg %a.arg, i32 inreg %b.arg) {
25882588
; GFX11-NEXT: v_rcp_f32_e32 v1, v1
25892589
; GFX11-NEXT: s_waitcnt_depctr 0xfff
25902590
; GFX11-NEXT: v_fma_mixlo_f16 v0, s0, v0, 0 op_sel_hi:[1,0,0]
2591-
; GFX11-NEXT: v_fma_mixlo_f16 v1, s0, v1, 0 op_sel:[1,0,0] op_sel_hi:[1,0,0]
2591+
; GFX11-NEXT: v_fma_mixlo_f16 v1, s3, v1, 0 op_sel_hi:[1,0,0]
25922592
; GFX11-NEXT: v_div_fixup_f16 v0, v0, s1, s0
25932593
; GFX11-NEXT: v_div_fixup_f16 v1, v1, s2, s3
25942594
; GFX11-NEXT: v_pack_b32_f16 v0, v0, v1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/madmix-constant-bus-violation.mir

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select,machineverifier -o - %s | FileCheck -check-prefixes=GFX9 %s
3+
4+
---
5+
name: foo
6+
legalized: true
7+
regBankSelected: true
8+
machineFunctionInfo:
9+
mode:
10+
fp32-output-denormals: false
11+
fp32-input-denormals: false
12+
body: |
13+
bb.0:
14+
; GFX9-LABEL: name: foo
15+
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
16+
; GFX9-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
17+
; GFX9-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16
18+
; GFX9-NEXT: [[S_LSHR_B32_:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY]], [[S_MOV_B32_]], implicit-def dead $scc
19+
; GFX9-NEXT: [[S_LSHR_B32_1:%[0-9]+]]:sreg_32 = S_LSHR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def dead $scc
20+
; GFX9-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_LSHR_B32_]]
21+
; GFX9-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_LSHR_B32_1]]
22+
; GFX9-NEXT: [[V_CVT_F32_F16_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_CVT_F32_F16_e64 0, [[COPY3]], 0, 0, implicit $mode, implicit $exec
23+
; GFX9-NEXT: [[V_RCP_F32_e64_:%[0-9]+]]:vgpr_32 = nofpexcept V_RCP_F32_e64 0, [[V_CVT_F32_F16_e64_]], 0, 0, implicit $mode, implicit $exec
24+
; GFX9-NEXT: [[V_MAD_MIX_F32_:%[0-9]+]]:vgpr_32 = V_MAD_MIX_F32 9, [[COPY3]], 0, [[V_RCP_F32_e64_]], 8, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
25+
; GFX9-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[V_MAD_MIX_F32_]], implicit $exec
26+
; GFX9-NEXT: $sgpr0 = COPY [[V_READFIRSTLANE_B32_]]
27+
; GFX9-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
28+
%0:sgpr(s32) = COPY $sgpr0
29+
%1:sgpr(s32) = COPY $sgpr1
30+
%2:sgpr(s32) = G_CONSTANT i32 16
31+
%3:sgpr(s32) = G_LSHR %0:sgpr, %2:sgpr(s32)
32+
%4:sgpr(s16) = G_TRUNC %3:sgpr(s32)
33+
%5:sgpr(s32) = G_LSHR %1:sgpr, %2:sgpr(s32)
34+
%6:sgpr(s16) = G_TRUNC %5:sgpr(s32)
35+
%7:vgpr(s16) = COPY %4:sgpr(s16)
36+
%8:vgpr(s32) = G_FPEXT %7:vgpr(s16)
37+
%9:vgpr(s16) = COPY %6:sgpr(s16)
38+
%10:vgpr(s32) = G_FPEXT %9:vgpr(s16)
39+
%11:vgpr(s32) = G_FNEG %10:vgpr
40+
%12:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %10:vgpr(s32)
41+
%13:vgpr(s32) = G_FMAD %11:vgpr, %12:vgpr, %8:vgpr
42+
%14:sgpr(s32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), %13:vgpr(s32)
43+
$sgpr0 = COPY %14:sgpr(s32)
44+
SI_RETURN_TO_EPILOG implicit $sgpr0
45+
...

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