@@ -776,27 +776,24 @@ static void getICMPOperandsForBranch(MachineInstr &MI, MachineIRBuilder &MIB,
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bool RISCVInstructionSelector::selectSelect (MachineInstr &MI,
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MachineIRBuilder &MIB,
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MachineRegisterInfo &MRI) const {
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- assert (MI. getOpcode () == TargetOpcode::G_SELECT );
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+ auto &SelectMI = cast<GSelect>(MI );
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// If MI is a G_SELECT(G_ICMP(tst, A, B), C, D) then we can use (A, B, tst)
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// as the (LHS, RHS, CC) of the Select_GPR_Using_CC_GPR.
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- Register MIOp1Reg = MI.getOperand (1 ).getReg ();
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- bool Op1IsICMP = mi_match (MIOp1Reg, MRI, m_GICmp (m_Pred (), m_Reg (), m_Reg ()));
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- RISCVCC::CondCode CC;
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- Register LHS, RHS;
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- if (Op1IsICMP)
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- getICMPOperandsForBranch (*MRI.getVRegDef (MIOp1Reg), MIB, MRI, CC, LHS, RHS);
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-
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- Register Op1 = Op1IsICMP ? LHS : MI.getOperand (1 ).getReg ();
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- Register Op2 = Op1IsICMP ? RHS : RISCV::X0;
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- unsigned Op3 = Op1IsICMP ? CC : RISCVCC::COND_NE;
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+ Register LHS = SelectMI.getCondReg ();
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+ Register RHS = RISCV::X0;
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+ RISCVCC::CondCode CC = RISCVCC::COND_NE;
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+
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+ if (mi_match (LHS, MRI, m_GICmp (m_Pred (), m_Reg (), m_Reg ())))
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+ getICMPOperandsForBranch (*MRI.getVRegDef (LHS), MIB, MRI, CC, LHS, RHS);
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+
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MachineInstr *Result = MIB.buildInstr (RISCV::Select_GPR_Using_CC_GPR)
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- .addDef (MI. getOperand ( 0 ). getReg ())
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- .addReg (Op1 )
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- .addReg (Op2 )
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- .addImm (Op3 )
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- .addReg (MI. getOperand ( 2 ). getReg ())
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- .addReg (MI. getOperand ( 3 ). getReg ());
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+ .addDef (SelectMI. getReg (0 ))
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+ .addReg (LHS )
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+ .addReg (RHS )
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+ .addImm (CC )
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+ .addReg (SelectMI. getTrueReg ())
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+ .addReg (SelectMI. getFalseReg ());
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MI.eraseFromParent ();
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return constrainSelectedInstRegOperands (*Result, TII, TRI, RBI);
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}
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