@@ -50824,37 +50824,18 @@ static SDValue combineFMulcFCMulc(SDNode *N, SelectionDAG &DAG,
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SDValue RHS = N->getOperand(1);
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int CombineOpcode =
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N->getOpcode() == X86ISD::VFCMULC ? X86ISD::VFMULC : X86ISD::VFCMULC;
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- auto isConjugationConstant = [](const Constant *c) {
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- if (const auto *CI = dyn_cast<ConstantInt>(c)) {
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- APInt ConjugationInt32 = APInt(32, 0x80000000, true);
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- APInt ConjugationInt64 = APInt(64, 0x8000000080000000ULL, true);
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- switch (CI->getBitWidth()) {
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- case 16:
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- return false;
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- case 32:
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- return CI->getValue() == ConjugationInt32;
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- case 64:
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- return CI->getValue() == ConjugationInt64;
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- default:
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- llvm_unreachable("Unexpected bit width");
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- }
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- }
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- if (const auto *CF = dyn_cast<ConstantFP>(c))
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- return CF->getType()->isFloatTy() && CF->isNegativeZeroValue();
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- return false;
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- };
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auto combineConjugation = [&](SDValue &r) {
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if (LHS->getOpcode() == ISD::BITCAST && RHS.hasOneUse()) {
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SDValue XOR = LHS.getOperand(0);
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if (XOR->getOpcode() == ISD::XOR && XOR.hasOneUse()) {
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- SDValue XORRHS = XOR.getOperand(1);
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- if (XORRHS.getOpcode() == ISD::BITCAST && XORRHS.hasOneUse())
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- XORRHS = XORRHS.getOperand(0 );
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- if (XORRHS.getOpcode() == X86ISD::VBROADCAST_LOAD &&
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- XORRHS.getOperand(1).getNumOperands()) {
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- ConstantPoolSDNode *CP =
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- dyn_cast<ConstantPoolSDNode> (XORRHS.getOperand(1).getOperand(0));
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- if (CP && isConjugationConstant(CP->getConstVal() )) {
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+ KnownBits XORRHS = DAG.computeKnownBits( XOR.getOperand(1) );
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+ if (XORRHS.isConstant()) {
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+ APInt ConjugationInt32 = APInt(32, 0x80000000, true );
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+ APInt ConjugationInt64 = APInt(64, 0x8000000080000000ULL, true);
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+ if (( XORRHS.getBitWidth() == 32 &&
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+ XORRHS.getConstant() == ConjugationInt32) ||
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+ (XORRHS.getBitWidth() == 64 &&
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+ XORRHS.getConstant() == ConjugationInt64 )) {
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SelectionDAG::FlagInserter FlagsInserter(DAG, N);
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SDValue I2F = DAG.getBitcast(VT, LHS.getOperand(0).getOperand(0));
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SDValue FCMulC = DAG.getNode(CombineOpcode, SDLoc(N), VT, RHS, I2F);
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