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Move the SIDefines helper functions for MCExpr cases to its own util header, add comments with explanations
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3 files changed

+86
-66
lines changed

3 files changed

+86
-66
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Lines changed: 2 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,7 @@
2929
#include "TargetInfo/AMDGPUTargetInfo.h"
3030
#include "Utils/AMDGPUBaseInfo.h"
3131
#include "Utils/AMDKernelCodeTUtils.h"
32+
#include "Utils/SIDefinesUtils.h"
3233
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
3334
#include "llvm/BinaryFormat/ELF.h"
3435
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -1194,30 +1195,6 @@ static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD,
11941195
getLdsDwGranularity(ST) * sizeof(uint32_t)));
11951196
}
11961197

1197-
static constexpr std::pair<unsigned, unsigned> getShiftMask(unsigned Value) {
1198-
unsigned Shift = 0;
1199-
unsigned Mask = 0;
1200-
1201-
Mask = ~Value;
1202-
for (; !(Mask & 1); Shift++, Mask >>= 1) {
1203-
}
1204-
1205-
return std::make_pair(Shift, Mask);
1206-
}
1207-
1208-
static const MCExpr *MaskShiftSet(const MCExpr *Val, uint32_t Mask,
1209-
uint32_t Shift, MCContext &Ctx) {
1210-
if (Mask) {
1211-
const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx);
1212-
Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx);
1213-
}
1214-
if (Shift) {
1215-
const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx);
1216-
Val = MCBinaryExpr::createShl(Val, ShiftExpr, Ctx);
1217-
}
1218-
return Val;
1219-
}
1220-
12211198
// This is the equivalent of EmitProgramInfoSI above, but for when the OS type
12221199
// is AMDPAL. It stores each compute/SPI register setting and other PAL
12231200
// metadata items into the PALMD::Metadata, combining with any provided by the
@@ -1249,7 +1226,7 @@ void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
12491226
MCBinaryExpr::createGT(CurrentProgramInfo.ScratchBlocks,
12501227
MCConstantExpr::create(0, Ctx), Ctx);
12511228
auto [Shift, Mask] = getShiftMask(C_00B84C_SCRATCH_EN);
1252-
MD->setRsrc2(CC, MaskShiftSet(HasScratchBlocks, Mask, Shift, Ctx), Ctx);
1229+
MD->setRsrc2(CC, maskShiftSet(HasScratchBlocks, Mask, Shift, Ctx), Ctx);
12531230
}
12541231
} else {
12551232
MD->setHwStage(CC, ".debug_mode", (bool)CurrentProgramInfo.DebugMode);

‎llvm/lib/Target/AMDGPU/Utils/AMDKernelCodeTUtils.cpp

Lines changed: 5 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#include "AMDKernelCodeT.h"
1515
#include "SIDefines.h"
1616
#include "Utils/AMDGPUBaseInfo.h"
17+
#include "Utils/SIDefinesUtils.h"
1718
#include "llvm/ADT/IndexedMap.h"
1819
#include "llvm/ADT/StringRef.h"
1920
#include "llvm/MC/MCContext.h"
@@ -220,43 +221,6 @@ static int get_amd_kernel_code_t_FieldIndex(StringRef name) {
220221
return map.lookup(name) - 1; // returns -1 if not found
221222
}
222223

223-
static constexpr std::pair<unsigned, unsigned> getShiftMask(unsigned Value) {
224-
unsigned Shift = 0;
225-
unsigned Mask = 0;
226-
227-
Mask = ~Value;
228-
for (; !(Mask & 1); Shift++, Mask >>= 1) {
229-
}
230-
231-
return std::make_pair(Shift, Mask);
232-
}
233-
234-
static const MCExpr *MaskShiftSet(const MCExpr *Val, uint32_t Mask,
235-
uint32_t Shift, MCContext &Ctx) {
236-
if (Mask) {
237-
const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx);
238-
Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx);
239-
}
240-
if (Shift) {
241-
const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx);
242-
Val = MCBinaryExpr::createShl(Val, ShiftExpr, Ctx);
243-
}
244-
return Val;
245-
}
246-
247-
static const MCExpr *MaskShiftGet(const MCExpr *Val, uint32_t Mask,
248-
uint32_t Shift, MCContext &Ctx) {
249-
if (Shift) {
250-
const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx);
251-
Val = MCBinaryExpr::createLShr(Val, ShiftExpr, Ctx);
252-
}
253-
if (Mask) {
254-
const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx);
255-
Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx);
256-
}
257-
return Val;
258-
}
259-
260224
class PrintField {
261225
public:
262226
template <typename T, T AMDGPUMCKernelCodeT::*ptr,
@@ -305,10 +269,10 @@ static ArrayRef<PrintFx> getPrinterTable() {
305269
const MCExpr *Value; \
306270
if (PGMType == 0) { \
307271
Value = \
308-
MaskShiftGet(C.compute_pgm_resource1_registers, Mask, Shift, Ctx); \
272+
maskShiftGet(C.compute_pgm_resource1_registers, Mask, Shift, Ctx); \
309273
} else { \
310274
Value = \
311-
MaskShiftGet(C.compute_pgm_resource2_registers, Mask, Shift, Ctx); \
275+
maskShiftGet(C.compute_pgm_resource2_registers, Mask, Shift, Ctx); \
312276
} \
313277
int64_t Val; \
314278
if (Value->evaluateAsAbsolute(Val)) \
@@ -392,7 +356,7 @@ static ArrayRef<ParseFx> getParserTable() {
392356
if (!parseExpr(MCParser, Value, Err)) \
393357
return false; \
394358
auto [Shift, Mask] = getShiftMask(Complement); \
395-
Value = MaskShiftSet(Value, Mask, Shift, Ctx); \
359+
Value = maskShiftSet(Value, Mask, Shift, Ctx); \
396360
const MCExpr *Compl = MCConstantExpr::create(Complement, Ctx); \
397361
if (PGMType == 0) { \
398362
C.compute_pgm_resource1_registers = MCBinaryExpr::createAnd( \
@@ -542,7 +506,7 @@ void AMDGPUMCKernelCodeT::EmitKernelCodeT(MCStreamer &OS, MCContext &Ctx) {
542506
const MCExpr *CodeProps = MCConstantExpr::create(code_properties, Ctx);
543507
CodeProps = MCBinaryExpr::createOr(
544508
CodeProps,
545-
MaskShiftSet(is_dynamic_callstack,
509+
maskShiftSet(is_dynamic_callstack,
546510
(1 << AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_WIDTH) - 1,
547511
AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK_SHIFT, Ctx),
548512
Ctx);

‎llvm/lib/Target/AMDGPU/Utils/SIDefinesUtils.h

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
//===-- SIDefines.h - SI Helper Functions -----------------------*- C++ -*-===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
/// \file - utility functions for the SIDefines and its common uses.
8+
//
9+
//===----------------------------------------------------------------------===//
10+
11+
#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_SIDEFINESUTILS_H
12+
#define LLVM_LIB_TARGET_AMDGPU_UTILS_SIDEFINESUTILS_H
13+
14+
#include "llvm/MC/MCExpr.h"
15+
#include <utility>
16+
17+
namespace llvm {
18+
class MCContext;
19+
namespace AMDGPU {
20+
21+
/// Deduce the least significant bit aligned shift and mask values for a binary
22+
/// Complement \p Value (as they're defined in SIDefines.h as C_*) as a returned
23+
/// pair<shift, mask>. That is to say \p Value == ~(mask << shift)
24+
///
25+
/// For example, given C_00B848_FWD_PROGRESS (i.e., 0x7FFFFFFF) from
26+
/// SIDefines.h, this will return the pair as (31,1).
27+
constexpr inline std::pair<unsigned, unsigned> getShiftMask(unsigned Value) {
28+
unsigned Shift = 0;
29+
unsigned Mask = 0;
30+
31+
Mask = ~Value;
32+
for (; !(Mask & 1); Shift++, Mask >>= 1) {
33+
}
34+
35+
return std::make_pair(Shift, Mask);
36+
}
37+
38+
/// Provided with the MCExpr * \p Val, uint32 \p Mask and \p Shift, will return
39+
/// the masked and left shifted, in said order of operations, MCExpr * created
40+
/// within the MCContext \p Ctx.
41+
///
42+
/// For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr
43+
/// * will be the equivalent of (Val & 0xf) << 6
44+
inline const MCExpr *maskShiftSet(const MCExpr *Val, uint32_t Mask,
45+
uint32_t Shift, MCContext &Ctx) {
46+
if (Mask) {
47+
const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx);
48+
Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx);
49+
}
50+
if (Shift) {
51+
const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx);
52+
Val = MCBinaryExpr::createShl(Val, ShiftExpr, Ctx);
53+
}
54+
return Val;
55+
}
56+
57+
/// Provided with the MCExpr * \p Val, uint32 \p Mask and \p Shift, will return
58+
/// the right shifted and masked, in said order of operations, MCExpr * created
59+
/// within the MCContext \p Ctx.
60+
///
61+
/// For example, given MCExpr *Val, Mask == 0xf, Shift == 6 the returned MCExpr
62+
/// * will be the equivalent of (Val >> 6) & 0xf
63+
inline const MCExpr *maskShiftGet(const MCExpr *Val, uint32_t Mask,
64+
uint32_t Shift, MCContext &Ctx) {
65+
if (Shift) {
66+
const MCExpr *ShiftExpr = MCConstantExpr::create(Shift, Ctx);
67+
Val = MCBinaryExpr::createLShr(Val, ShiftExpr, Ctx);
68+
}
69+
if (Mask) {
70+
const MCExpr *MaskExpr = MCConstantExpr::create(Mask, Ctx);
71+
Val = MCBinaryExpr::createAnd(Val, MaskExpr, Ctx);
72+
}
73+
return Val;
74+
}
75+
76+
} // end namespace AMDGPU
77+
} // end namespace llvm
78+
79+
#endif // LLVM_LIB_TARGET_AMDGPU_UTILS_SIDEFINESUTILS_H

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