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- Support vectors in lowerFAbs
- Simplify legality predicates

Author: Him188

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

@@ -8770,9 +8770,10 @@ LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
   LLT Ty = MRI.getType(DstReg);
 
   // Reset sign bit
-  MIRBuilder.buildAnd(DstReg, SrcReg,
-                      MIRBuilder.buildConstant(
-                          Ty, APInt::getSignedMaxValue(Ty.getSizeInBits())));
+  MIRBuilder.buildAnd(
+      DstReg, SrcReg,
+      MIRBuilder.buildConstant(
+          Ty, APInt::getSignedMaxValue(Ty.getScalarSizeInBits())));
 
   MI.eraseFromParent();
   return Legalized;

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -89,6 +89,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   const bool HasFP16 = ST.hasFullFP16();
   const LLT &MinFPScalar = HasFP16 ? s16 : s32;
 
+  // A legality predicate that returns true if the subtarget has FP16 support.
+  // To be used in combination with other predicates, e.g:
+  //     .legalIf(all(hasFP16(), typeInSet(0, {v8s16, v4s16})))
+  const auto hasFP16 = [=]() -> LegalityPredicate {
+    return [=](const LegalityQuery &) { return HasFP16; };
+  };
+
   const bool HasCSSC = ST.hasCSSC();
   const bool HasRCPC3 = ST.hasRCPC3();
 
@@ -260,12 +267,12 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
 
   getActionDefinitionsBuilder(G_FABS)
       .legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
-      .legalIf([=](const LegalityQuery &Query) {
-        const auto &Ty = Query.Types[0];
-        return (Ty == v8s16 || Ty == v4s16) && HasFP16;
-      })
-      .lowerFor({s128})
+      .legalIf(all(hasFP16(), typeInSet(0, {v8s16, v4s16})))
+      // TODO: Lower supports 128-bit types but G_AND generated by Lower does
+      // not yet.
+      //       When it does, we can remove scalarizeIf.
       .scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
+      .lowerIf(scalarOrEltWiderThan(0, 64))
       .minScalarOrElt(0, MinFPScalar)
       .clampNumElements(0, v4s16, v8s16)
       .clampNumElements(0, v2s32, v4s32)

llvm/test/CodeGen/AArch64/fabs-fp128.ll

@@ -78,5 +78,93 @@ entry:
   ret <2 x fp128> %c
 }
 
+define <3 x fp128> @fabs_v3f128(<3 x fp128> %a) {
+; CHECK-SD-LABEL: fabs_v3f128:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    stp q0, q1, [sp, #-48]!
+; CHECK-SD-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT:    ldrb w8, [sp, #15]
+; CHECK-SD-NEXT:    str q2, [sp, #32]
+; CHECK-SD-NEXT:    and w8, w8, #0x7f
+; CHECK-SD-NEXT:    strb w8, [sp, #15]
+; CHECK-SD-NEXT:    ldrb w8, [sp, #31]
+; CHECK-SD-NEXT:    and w8, w8, #0x7f
+; CHECK-SD-NEXT:    strb w8, [sp, #31]
+; CHECK-SD-NEXT:    ldrb w8, [sp, #47]
+; CHECK-SD-NEXT:    ldp q0, q1, [sp]
+; CHECK-SD-NEXT:    and w8, w8, #0x7f
+; CHECK-SD-NEXT:    strb w8, [sp, #47]
+; CHECK-SD-NEXT:    ldr q2, [sp, #32]
+; CHECK-SD-NEXT:    add sp, sp, #48
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fabs_v3f128:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    mov x8, v0.d[1]
+; CHECK-GI-NEXT:    mov x9, v1.d[1]
+; CHECK-GI-NEXT:    mov x10, v2.d[1]
+; CHECK-GI-NEXT:    mov v0.d[0], v0.d[0]
+; CHECK-GI-NEXT:    mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT:    mov v2.d[0], v2.d[0]
+; CHECK-GI-NEXT:    and x8, x8, #0x7fffffffffffffff
+; CHECK-GI-NEXT:    and x9, x9, #0x7fffffffffffffff
+; CHECK-GI-NEXT:    and x10, x10, #0x7fffffffffffffff
+; CHECK-GI-NEXT:    mov v0.d[1], x8
+; CHECK-GI-NEXT:    mov v1.d[1], x9
+; CHECK-GI-NEXT:    mov v2.d[1], x10
+; CHECK-GI-NEXT:    ret
+entry:
+  %c = call <3 x fp128> @llvm.fabs.v3f128(<3 x fp128> %a)
+  ret <3 x fp128> %c
+}
+
+define <4 x fp128> @fabs_v4f128(<4 x fp128> %a) {
+; CHECK-SD-LABEL: fabs_v4f128:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    stp q0, q1, [sp, #-64]!
+; CHECK-SD-NEXT:    .cfi_def_cfa_offset 64
+; CHECK-SD-NEXT:    ldrb w8, [sp, #15]
+; CHECK-SD-NEXT:    stp q2, q3, [sp, #32]
+; CHECK-SD-NEXT:    and w8, w8, #0x7f
+; CHECK-SD-NEXT:    strb w8, [sp, #15]
+; CHECK-SD-NEXT:    ldrb w8, [sp, #31]
+; CHECK-SD-NEXT:    and w8, w8, #0x7f
+; CHECK-SD-NEXT:    strb w8, [sp, #31]
+; CHECK-SD-NEXT:    ldrb w8, [sp, #47]
+; CHECK-SD-NEXT:    ldp q0, q1, [sp]
+; CHECK-SD-NEXT:    and w8, w8, #0x7f
+; CHECK-SD-NEXT:    strb w8, [sp, #47]
+; CHECK-SD-NEXT:    ldrb w8, [sp, #63]
+; CHECK-SD-NEXT:    and w8, w8, #0x7f
+; CHECK-SD-NEXT:    strb w8, [sp, #63]
+; CHECK-SD-NEXT:    ldp q2, q3, [sp, #32]
+; CHECK-SD-NEXT:    add sp, sp, #64
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: fabs_v4f128:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    mov x8, v0.d[1]
+; CHECK-GI-NEXT:    mov v7.d[0], v0.d[0]
+; CHECK-GI-NEXT:    mov x9, v1.d[1]
+; CHECK-GI-NEXT:    mov x10, v2.d[1]
+; CHECK-GI-NEXT:    mov x11, v3.d[1]
+; CHECK-GI-NEXT:    mov v1.d[0], v1.d[0]
+; CHECK-GI-NEXT:    mov v2.d[0], v2.d[0]
+; CHECK-GI-NEXT:    mov v3.d[0], v3.d[0]
+; CHECK-GI-NEXT:    and x8, x8, #0x7fffffffffffffff
+; CHECK-GI-NEXT:    mov v7.d[1], x8
+; CHECK-GI-NEXT:    and x8, x9, #0x7fffffffffffffff
+; CHECK-GI-NEXT:    and x9, x10, #0x7fffffffffffffff
+; CHECK-GI-NEXT:    and x10, x11, #0x7fffffffffffffff
+; CHECK-GI-NEXT:    mov v1.d[1], x8
+; CHECK-GI-NEXT:    mov v2.d[1], x9
+; CHECK-GI-NEXT:    mov v3.d[1], x10
+; CHECK-GI-NEXT:    mov v0.16b, v7.16b
+; CHECK-GI-NEXT:    ret
+entry:
+  %c = call <4 x fp128> @llvm.fabs.v4f128(<4 x fp128> %a)
+  ret <4 x fp128> %c
+}
+
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; CHECK: {{.*}}