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[AMDGPU] prevent shrinking udiv/urem if either operand is in (SignedMax,UnsignedMax] (#116733)
Do this by using ComputeKnownBits and checking for !isNonNegative and isUnsigned. This rejects shrinking unsigned div/rem if operands exceed smax_bitwidth since we know NumSignBits will be always 0.
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‎llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

Lines changed: 29 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1193,19 +1193,35 @@ int AMDGPUCodeGenPrepareImpl::getDivNumBits(BinaryOperator &I, Value *Num,
11931193
Value *Den, unsigned AtLeast,
11941194
bool IsSigned) const {
11951195
const DataLayout &DL = Mod->getDataLayout();
1196-
unsigned LHSSignBits = ComputeNumSignBits(Num, DL, 0, AC, &I);
1197-
if (LHSSignBits < AtLeast)
1198-
return -1;
1199-
1200-
unsigned RHSSignBits = ComputeNumSignBits(Den, DL, 0, AC, &I);
1201-
if (RHSSignBits < AtLeast)
1202-
return -1;
1203-
1204-
unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1205-
unsigned DivBits = Num->getType()->getScalarSizeInBits() - SignBits;
1206-
if (IsSigned)
1207-
++DivBits;
1208-
return DivBits;
1196+
if (IsSigned) {
1197+
unsigned LHSSignBits = ComputeNumSignBits(Num, DL, 0, AC, &I);
1198+
if (LHSSignBits < AtLeast)
1199+
return -1;
1200+
1201+
unsigned RHSSignBits = ComputeNumSignBits(Den, DL, 0, AC, &I);
1202+
if (RHSSignBits < AtLeast)
1203+
return -1;
1204+
1205+
unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1206+
unsigned DivBits = Num->getType()->getScalarSizeInBits() - SignBits;
1207+
return DivBits + 1;
1208+
} else {
1209+
KnownBits Known = computeKnownBits(Num, DL, 0, AC, &I);
1210+
// We know all bits are used for division for Num or Den in range
1211+
// (SignedMax, UnsignedMax]
1212+
if (Known.isNegative() || !Known.isNonNegative())
1213+
return -1;
1214+
unsigned LHSSignBits = Known.countMinLeadingZeros();
1215+
1216+
Known = computeKnownBits(Den, DL, 0, AC, &I);
1217+
if (Known.isNegative() || !Known.isNonNegative())
1218+
return -1;
1219+
unsigned RHSSignBits = Known.countMinLeadingZeros();
1220+
1221+
unsigned SignBits = std::min(LHSSignBits, RHSSignBits);
1222+
unsigned DivBits = Num->getType()->getScalarSizeInBits() - SignBits;
1223+
return DivBits;
1224+
}
12091225
}
12101226

12111227
// The fractional part of a float is enough to accurately represent up to

‎llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll

Lines changed: 98 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9999,3 +9999,101 @@ define <2 x i64> @v_udiv_i64_exact(<2 x i64> %num) {
99999999
%result = udiv exact <2 x i64> %num, <i64 4096, i64 1024>
1000010000
ret <2 x i64> %result
1000110001
}
10002+
10003+
define i64 @udiv_i64_gt_smax(i8 %size) {
10004+
; GFX6-LABEL: udiv_i64_gt_smax:
10005+
; GFX6: ; %bb.0:
10006+
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10007+
; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8
10008+
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
10009+
; GFX6-NEXT: v_not_b32_e32 v1, v1
10010+
; GFX6-NEXT: v_not_b32_e32 v0, v0
10011+
; GFX6-NEXT: s_mov_b32 s4, 0xcccccccd
10012+
; GFX6-NEXT: v_mul_lo_u32 v3, v1, s4
10013+
; GFX6-NEXT: v_mul_hi_u32 v4, v0, s4
10014+
; GFX6-NEXT: s_mov_b32 s6, 0xcccccccc
10015+
; GFX6-NEXT: v_mul_hi_u32 v5, v1, s4
10016+
; GFX6-NEXT: v_mul_hi_u32 v2, v0, s6
10017+
; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
10018+
; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v4
10019+
; GFX6-NEXT: v_addc_u32_e32 v4, vcc, 0, v5, vcc
10020+
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v3
10021+
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
10022+
; GFX6-NEXT: v_mul_lo_u32 v2, v1, s6
10023+
; GFX6-NEXT: v_mul_hi_u32 v1, v1, s6
10024+
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v4, v0
10025+
; GFX6-NEXT: v_addc_u32_e64 v3, s[4:5], 0, 0, vcc
10026+
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
10027+
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
10028+
; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 3
10029+
; GFX6-NEXT: v_lshrrev_b32_e32 v1, 3, v1
10030+
; GFX6-NEXT: s_setpc_b64 s[30:31]
10031+
;
10032+
; GFX9-LABEL: udiv_i64_gt_smax:
10033+
; GFX9: ; %bb.0:
10034+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10035+
; GFX9-NEXT: v_mov_b32_e32 v1, 31
10036+
; GFX9-NEXT: v_not_b32_sdwa v4, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0
10037+
; GFX9-NEXT: s_mov_b32 s4, 0xcccccccd
10038+
; GFX9-NEXT: v_ashrrev_i32_sdwa v1, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
10039+
; GFX9-NEXT: v_mul_hi_u32 v0, v4, s4
10040+
; GFX9-NEXT: v_not_b32_e32 v5, v1
10041+
; GFX9-NEXT: v_mov_b32_e32 v1, 0
10042+
; GFX9-NEXT: s_mov_b32 s6, 0xcccccccc
10043+
; GFX9-NEXT: v_mad_u64_u32 v[2:3], s[4:5], v5, s4, v[0:1]
10044+
; GFX9-NEXT: v_mov_b32_e32 v6, v3
10045+
; GFX9-NEXT: v_mov_b32_e32 v3, v1
10046+
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v4, s6, v[2:3]
10047+
; GFX9-NEXT: v_mov_b32_e32 v0, v1
10048+
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, v6, v0
10049+
; GFX9-NEXT: v_addc_co_u32_e64 v1, s[4:5], 0, 0, vcc
10050+
; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, s6, v[0:1]
10051+
; GFX9-NEXT: v_alignbit_b32 v0, v1, v0, 3
10052+
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 3, v1
10053+
; GFX9-NEXT: s_setpc_b64 s[30:31]
10054+
%esize = sext i8 %size to i64
10055+
%minus = sub nuw nsw i64 -1, %esize
10056+
%div = udiv i64 %minus, 10
10057+
ret i64 %div
10058+
}
10059+
10060+
define i64 @udiv_i64_9divbits(i8 %size) {
10061+
; GFX6-LABEL: udiv_i64_9divbits:
10062+
; GFX6: ; %bb.0:
10063+
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10064+
; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0
10065+
; GFX6-NEXT: v_add_i32_e32 v0, vcc, 1, v0
10066+
; GFX6-NEXT: v_cvt_f32_u32_e32 v0, v0
10067+
; GFX6-NEXT: s_mov_b32 s4, 0x41200000
10068+
; GFX6-NEXT: v_mul_f32_e32 v1, 0x3dcccccd, v0
10069+
; GFX6-NEXT: v_trunc_f32_e32 v1, v1
10070+
; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v1
10071+
; GFX6-NEXT: v_mad_f32 v0, -v1, s4, v0
10072+
; GFX6-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
10073+
; GFX6-NEXT: v_mov_b32_e32 v1, 0
10074+
; GFX6-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc
10075+
; GFX6-NEXT: v_and_b32_e32 v0, 0x1ff, v0
10076+
; GFX6-NEXT: s_setpc_b64 s[30:31]
10077+
;
10078+
; GFX9-LABEL: udiv_i64_9divbits:
10079+
; GFX9: ; %bb.0:
10080+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10081+
; GFX9-NEXT: v_mov_b32_e32 v1, 1
10082+
; GFX9-NEXT: v_add_u32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
10083+
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0
10084+
; GFX9-NEXT: s_mov_b32 s4, 0x41200000
10085+
; GFX9-NEXT: v_mul_f32_e32 v1, 0x3dcccccd, v0
10086+
; GFX9-NEXT: v_trunc_f32_e32 v1, v1
10087+
; GFX9-NEXT: v_cvt_u32_f32_e32 v2, v1
10088+
; GFX9-NEXT: v_mad_f32 v0, -v1, s4, v0
10089+
; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4
10090+
; GFX9-NEXT: v_mov_b32_e32 v1, 0
10091+
; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v2, vcc
10092+
; GFX9-NEXT: v_and_b32_e32 v0, 0x1ff, v0
10093+
; GFX9-NEXT: s_setpc_b64 s[30:31]
10094+
%zextend = zext i8 %size to i64
10095+
%num = add nuw nsw i64 1, %zextend
10096+
%div = udiv i64 %num, 10
10097+
ret i64 %div
10098+
}
10099+

‎llvm/test/CodeGen/AMDGPU/bypass-div.ll

Lines changed: 115 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1021,8 +1021,116 @@ define i64 @sdiv64_known32(i64 %a, i64 %b) {
10211021
; GFX9-LABEL: sdiv64_known32:
10221022
; GFX9: ; %bb.0:
10231023
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1024+
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v1
1025+
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
1026+
; GFX9-NEXT: v_or_b32_e32 v5, v2, v0
1027+
; GFX9-NEXT: v_mov_b32_e32 v4, 0
1028+
; GFX9-NEXT: v_cmp_ne_u64_e32 vcc, 0, v[4:5]
1029+
; GFX9-NEXT: v_mov_b32_e32 v7, v1
1030+
; GFX9-NEXT: v_mov_b32_e32 v6, v3
1031+
; GFX9-NEXT: ; implicit-def: $vgpr4_vgpr5
1032+
; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc
1033+
; GFX9-NEXT: s_xor_b64 s[6:7], exec, s[4:5]
1034+
; GFX9-NEXT: s_cbranch_execz .LBB10_2
1035+
; GFX9-NEXT: ; %bb.1:
1036+
; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v6
1037+
; GFX9-NEXT: v_cvt_f32_u32_e32 v3, v0
1038+
; GFX9-NEXT: v_sub_co_u32_e32 v11, vcc, 0, v6
1039+
; GFX9-NEXT: v_subb_co_u32_e32 v12, vcc, 0, v0, vcc
1040+
; GFX9-NEXT: v_madmk_f32 v1, v3, 0x4f800000, v1
1041+
; GFX9-NEXT: v_rcp_f32_e32 v1, v1
1042+
; GFX9-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1
1043+
; GFX9-NEXT: v_mul_f32_e32 v3, 0x2f800000, v1
1044+
; GFX9-NEXT: v_trunc_f32_e32 v3, v3
1045+
; GFX9-NEXT: v_madmk_f32 v1, v3, 0xcf800000, v1
1046+
; GFX9-NEXT: v_cvt_u32_f32_e32 v10, v3
1047+
; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1
1048+
; GFX9-NEXT: v_mul_lo_u32 v5, v11, v10
1049+
; GFX9-NEXT: v_mul_lo_u32 v8, v12, v1
1050+
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v1, 0
1051+
; GFX9-NEXT: v_add3_u32 v8, v4, v5, v8
1052+
; GFX9-NEXT: v_mul_hi_u32 v9, v1, v3
1053+
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v1, v8, 0
1054+
; GFX9-NEXT: v_add_co_u32_e32 v13, vcc, v9, v4
1055+
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v10, v3, 0
1056+
; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v10, v8, 0
1057+
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
1058+
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v13, v3
1059+
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v4, vcc
1060+
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v9, vcc
1061+
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v8
1062+
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v4, vcc
1063+
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
1064+
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v10, v4, vcc
1065+
; GFX9-NEXT: v_mul_lo_u32 v5, v11, v13
1066+
; GFX9-NEXT: v_mul_lo_u32 v8, v12, v1
1067+
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v11, v1, 0
1068+
; GFX9-NEXT: v_add3_u32 v8, v4, v5, v8
1069+
; GFX9-NEXT: v_mad_u64_u32 v[4:5], s[4:5], v13, v8, 0
1070+
; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v1, v8, 0
1071+
; GFX9-NEXT: v_mul_hi_u32 v12, v1, v3
1072+
; GFX9-NEXT: v_mad_u64_u32 v[10:11], s[4:5], v13, v3, 0
1073+
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v12, v8
1074+
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v9, vcc
1075+
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v10
1076+
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v8, v11, vcc
1077+
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
1078+
; GFX9-NEXT: v_add_co_u32_e32 v3, vcc, v3, v4
1079+
; GFX9-NEXT: v_addc_co_u32_e32 v4, vcc, 0, v5, vcc
1080+
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v3
1081+
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v13, v4, vcc
1082+
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v7, v5, 0
1083+
; GFX9-NEXT: v_mul_hi_u32 v8, v7, v1
1084+
; GFX9-NEXT: v_add_co_u32_e32 v10, vcc, v8, v3
1085+
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, 0, v4, vcc
1086+
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v2, v1, 0
1087+
; GFX9-NEXT: v_mad_u64_u32 v[8:9], s[4:5], v2, v5, 0
1088+
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v10, v3
1089+
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v11, v4, vcc
1090+
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v9, vcc
1091+
; GFX9-NEXT: v_add_co_u32_e32 v1, vcc, v1, v8
1092+
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v3, vcc
1093+
; GFX9-NEXT: v_mul_lo_u32 v8, v0, v1
1094+
; GFX9-NEXT: v_mul_lo_u32 v9, v6, v5
1095+
; GFX9-NEXT: v_mad_u64_u32 v[3:4], s[4:5], v6, v1, 0
1096+
; GFX9-NEXT: v_add3_u32 v4, v4, v9, v8
1097+
; GFX9-NEXT: v_sub_u32_e32 v8, v2, v4
1098+
; GFX9-NEXT: v_sub_co_u32_e32 v3, vcc, v7, v3
1099+
; GFX9-NEXT: v_subb_co_u32_e64 v7, s[4:5], v8, v0, vcc
1100+
; GFX9-NEXT: v_sub_co_u32_e64 v8, s[4:5], v3, v6
1101+
; GFX9-NEXT: v_subbrev_co_u32_e64 v7, s[4:5], 0, v7, s[4:5]
1102+
; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v0
1103+
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
1104+
; GFX9-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v6
1105+
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5]
1106+
; GFX9-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v0
1107+
; GFX9-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5]
1108+
; GFX9-NEXT: v_add_co_u32_e64 v8, s[4:5], 2, v1
1109+
; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v4, vcc
1110+
; GFX9-NEXT: v_addc_co_u32_e64 v9, s[4:5], 0, v5, s[4:5]
1111+
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0
1112+
; GFX9-NEXT: v_add_co_u32_e64 v10, s[4:5], 1, v1
1113+
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc
1114+
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v3, v6
1115+
; GFX9-NEXT: v_addc_co_u32_e64 v11, s[4:5], 0, v5, s[4:5]
1116+
; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc
1117+
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, v2, v0
1118+
; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7
1119+
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v3, vcc
1120+
; GFX9-NEXT: v_cndmask_b32_e64 v7, v11, v9, s[4:5]
1121+
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
1122+
; GFX9-NEXT: v_cndmask_b32_e64 v0, v10, v8, s[4:5]
1123+
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
1124+
; GFX9-NEXT: v_cndmask_b32_e32 v4, v1, v0, vcc
1125+
; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
1126+
; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1
1127+
; GFX9-NEXT: .LBB10_2: ; %Flow
1128+
; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[6:7]
1129+
; GFX9-NEXT: s_cbranch_execz .LBB10_4
1130+
; GFX9-NEXT: ; %bb.3:
10241131
; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v3
10251132
; GFX9-NEXT: v_sub_u32_e32 v2, 0, v3
1133+
; GFX9-NEXT: v_mov_b32_e32 v5, 0
10261134
; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0
10271135
; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
10281136
; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0
@@ -1033,14 +1141,17 @@ define i64 @sdiv64_known32(i64 %a, i64 %b) {
10331141
; GFX9-NEXT: v_mul_lo_u32 v2, v0, v3
10341142
; GFX9-NEXT: v_add_u32_e32 v4, 1, v0
10351143
; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2
1036-
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
10371144
; GFX9-NEXT: v_sub_u32_e32 v2, v1, v3
1038-
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
1145+
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
10391146
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
1147+
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
10401148
; GFX9-NEXT: v_add_u32_e32 v2, 1, v0
10411149
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
1042-
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
1043-
; GFX9-NEXT: v_mov_b32_e32 v1, 0
1150+
; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v2, vcc
1151+
; GFX9-NEXT: .LBB10_4:
1152+
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
1153+
; GFX9-NEXT: v_mov_b32_e32 v0, v4
1154+
; GFX9-NEXT: v_mov_b32_e32 v1, v5
10441155
; GFX9-NEXT: s_setpc_b64 s[30:31]
10451156
%a.ext = ashr i64 %a, 32
10461157
%b.ext = ashr i64 %b, 32

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