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[AArch64][SME] Various tests should work with +sme, just as they do for +sve (#65260)
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‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1275,7 +1275,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
12751275
}
12761276
}
12771277

1278-
if (Subtarget->hasSVE()) {
1278+
if (Subtarget->hasSVEorSME()) {
12791279
for (auto VT : {MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64}) {
12801280
setOperationAction(ISD::BITREVERSE, VT, Custom);
12811281
setOperationAction(ISD::BSWAP, VT, Custom);
@@ -6245,9 +6245,9 @@ bool AArch64TargetLowering::useSVEForFixedLengthVectorVT(
62456245
break;
62466246
}
62476247

6248-
// All SVE implementations support NEON sized vectors.
6248+
// NEON-sized vectors can be emulated using SVE instructions.
62496249
if (OverrideNEON && (VT.is128BitVector() || VT.is64BitVector()))
6250-
return Subtarget->hasSVE();
6250+
return Subtarget->hasSVEorSME();
62516251

62526252
// Ensure NEON MVTs only belong to a single register class.
62536253
if (VT.getFixedSizeInBits() <= 128)

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 20 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -3971,7 +3971,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
39713971
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
39723972
Opc = AArch64::STRHui;
39733973
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
3974-
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
3974+
assert(Subtarget.hasSVEorSME() &&
3975+
"Unexpected register store without SVE store instructions");
39753976
Opc = AArch64::STR_PXI;
39763977
StackID = TargetStackID::ScalableVector;
39773978
}
@@ -4015,7 +4016,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40154016
AArch64::sube64, AArch64::subo64, FI, MMO);
40164017
return;
40174018
} else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
4018-
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
4019+
assert(Subtarget.hasSVEorSME() &&
4020+
"Unexpected register store without SVE store instructions");
40194021
Opc = AArch64::STR_ZXI;
40204022
StackID = TargetStackID::ScalableVector;
40214023
}
@@ -4038,7 +4040,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40384040
Offset = false;
40394041
} else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
40404042
AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
4041-
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
4043+
assert(Subtarget.hasSVEorSME() &&
4044+
"Unexpected register store without SVE store instructions");
40424045
Opc = AArch64::STR_ZZXI;
40434046
StackID = TargetStackID::ScalableVector;
40444047
}
@@ -4049,7 +4052,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40494052
Opc = AArch64::ST1Threev2d;
40504053
Offset = false;
40514054
} else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
4052-
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
4055+
assert(Subtarget.hasSVEorSME() &&
4056+
"Unexpected register store without SVE store instructions");
40534057
Opc = AArch64::STR_ZZZXI;
40544058
StackID = TargetStackID::ScalableVector;
40554059
}
@@ -4061,7 +4065,8 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
40614065
Offset = false;
40624066
} else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
40634067
AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
4064-
assert(Subtarget.hasSVE() && "Unexpected register store without SVE");
4068+
assert(Subtarget.hasSVEorSME() &&
4069+
"Unexpected register store without SVE store instructions");
40654070
Opc = AArch64::STR_ZZZZXI;
40664071
StackID = TargetStackID::ScalableVector;
40674072
}
@@ -4129,7 +4134,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
41294134
if (AArch64::FPR16RegClass.hasSubClassEq(RC))
41304135
Opc = AArch64::LDRHui;
41314136
else if (AArch64::PPRRegClass.hasSubClassEq(RC)) {
4132-
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
4137+
assert(Subtarget.hasSVEorSME() &&
4138+
"Unexpected register load without SVE load instructions");
41334139
Opc = AArch64::LDR_PXI;
41344140
StackID = TargetStackID::ScalableVector;
41354141
}
@@ -4173,7 +4179,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
41734179
AArch64::subo64, FI, MMO);
41744180
return;
41754181
} else if (AArch64::ZPRRegClass.hasSubClassEq(RC)) {
4176-
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
4182+
assert(Subtarget.hasSVEorSME() &&
4183+
"Unexpected register load without SVE load instructions");
41774184
Opc = AArch64::LDR_ZXI;
41784185
StackID = TargetStackID::ScalableVector;
41794186
}
@@ -4196,7 +4203,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
41964203
Offset = false;
41974204
} else if (AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
41984205
AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC)) {
4199-
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
4206+
assert(Subtarget.hasSVEorSME() &&
4207+
"Unexpected register load without SVE load instructions");
42004208
Opc = AArch64::LDR_ZZXI;
42014209
StackID = TargetStackID::ScalableVector;
42024210
}
@@ -4207,7 +4215,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
42074215
Opc = AArch64::LD1Threev2d;
42084216
Offset = false;
42094217
} else if (AArch64::ZPR3RegClass.hasSubClassEq(RC)) {
4210-
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
4218+
assert(Subtarget.hasSVEorSME() &&
4219+
"Unexpected register load without SVE load instructions");
42114220
Opc = AArch64::LDR_ZZZXI;
42124221
StackID = TargetStackID::ScalableVector;
42134222
}
@@ -4219,7 +4228,8 @@ void AArch64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
42194228
Offset = false;
42204229
} else if (AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
42214230
AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC)) {
4222-
assert(Subtarget.hasSVE() && "Unexpected register load without SVE");
4231+
assert(Subtarget.hasSVEorSME() &&
4232+
"Unexpected register load without SVE load instructions");
42234233
Opc = AArch64::LDR_ZZZZXI;
42244234
StackID = TargetStackID::ScalableVector;
42254235
}

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -402,10 +402,10 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
402402

403403
bool useSVEForFixedLengthVectors() const {
404404
if (!isNeonAvailable())
405-
return hasSVE();
405+
return hasSVEorSME();
406406

407407
// Prefer NEON unless larger SVE registers are available.
408-
return hasSVE() && getMinSVEVectorSizeInBits() >= 256;
408+
return hasSVEorSME() && getMinSVEVectorSizeInBits() >= 256;
409409
}
410410

411411
bool useSVEForFixedLengthVectors(EVT VT) const {

‎llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
33

44
define <vscale x 16 x i8> @extract_row_b(<vscale x 16 x i8> %zd, <vscale x 16 x i1> %pg, i32 %tileslice) {
55
; CHECK-LABEL: extract_row_b:

‎llvm/test/CodeGen/AArch64/sme-intrinsics-mova-insert.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s
33

44
define void @insert_row_b(i32 %tileslice, <vscale x 16 x i1> %pg,
55
; CHECK-LABEL: insert_row_b:

‎llvm/test/CodeGen/AArch64/sme-streaming-body.ll

Lines changed: 21 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -87,25 +87,29 @@ if.end:
8787
define <2 x i64> @locally_streaming_caller_no_callee(<2 x i64> %a) "aarch64_pstate_sm_body" nounwind {
8888
; CHECK-LABEL: locally_streaming_caller_no_callee:
8989
; CHECK: // %bb.0:
90-
; CHECK-NEXT: sub sp, sp, #80
91-
; CHECK-NEXT: stp d15, d14, [sp, #16] // 16-byte Folded Spill
92-
; CHECK-NEXT: stp d13, d12, [sp, #32] // 16-byte Folded Spill
93-
; CHECK-NEXT: stp d11, d10, [sp, #48] // 16-byte Folded Spill
94-
; CHECK-NEXT: stp d9, d8, [sp, #64] // 16-byte Folded Spill
95-
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
90+
; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
91+
; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill
92+
; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill
93+
; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill
94+
; CHECK-NEXT: str x29, [sp, #64] // 8-byte Folded Spill
95+
; CHECK-NEXT: addsvl sp, sp, #-1
96+
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
97+
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
9698
; CHECK-NEXT: smstart sm
97-
; CHECK-NEXT: adrp x8, .LCPI3_0
98-
; CHECK-NEXT: ldr q1, [sp] // 16-byte Folded Reload
99-
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_0]
100-
; CHECK-NEXT: add v0.2d, v1.2d, v0.2d
101-
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
99+
; CHECK-NEXT: index z0.d, #0, #1
100+
; CHECK-NEXT: ldr z1, [sp] // 16-byte Folded Reload
101+
; CHECK-NEXT: add z0.d, z0.d, z1.d
102+
; CHECK-NEXT: add z0.d, z0.d, #41 // =0x29
103+
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
102104
; CHECK-NEXT: smstop sm
103-
; CHECK-NEXT: ldp d9, d8, [sp, #64] // 16-byte Folded Reload
104-
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
105-
; CHECK-NEXT: ldp d11, d10, [sp, #48] // 16-byte Folded Reload
106-
; CHECK-NEXT: ldp d13, d12, [sp, #32] // 16-byte Folded Reload
107-
; CHECK-NEXT: ldp d15, d14, [sp, #16] // 16-byte Folded Reload
108-
; CHECK-NEXT: add sp, sp, #80
105+
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
106+
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
107+
; CHECK-NEXT: addsvl sp, sp, #1
108+
; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload
109+
; CHECK-NEXT: ldr x29, [sp, #64] // 8-byte Folded Reload
110+
; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload
111+
; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload
112+
; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload
109113
; CHECK-NEXT: ret
110114

111115
%add = add <2 x i64> %a, <i64 41, i64 42>;

‎llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -120,7 +120,7 @@ define void @streaming_compatible_caller_and_callee() "aarch64_pstate_sm_compati
120120
; Handle special cases here.
121121
;
122122

123-
define <2 x double> @streaming_compatible_with_neon_vectors(<2 x double> %arg) "aarch64_pstate_sm_compatible" nounwind #0 {
123+
define <2 x double> @streaming_compatible_with_neon_vectors(<2 x double> %arg) "aarch64_pstate_sm_compatible" nounwind {
124124
; CHECK-LABEL: streaming_compatible_with_neon_vectors:
125125
; CHECK: // %bb.0:
126126
; CHECK-NEXT: stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
@@ -166,7 +166,7 @@ define <2 x double> @streaming_compatible_with_neon_vectors(<2 x double> %arg) "
166166
}
167167
declare <2 x double> @normal_callee_vec_arg(<2 x double>)
168168

169-
define <vscale x 2 x double> @streaming_compatible_with_scalable_vectors(<vscale x 2 x double> %arg) "aarch64_pstate_sm_compatible" nounwind #0 {
169+
define <vscale x 2 x double> @streaming_compatible_with_scalable_vectors(<vscale x 2 x double> %arg) "aarch64_pstate_sm_compatible" nounwind {
170170
; CHECK-LABEL: streaming_compatible_with_scalable_vectors:
171171
; CHECK: // %bb.0:
172172
; CHECK-NEXT: str x29, [sp, #-32]! // 8-byte Folded Spill
@@ -258,7 +258,7 @@ define <vscale x 2 x double> @streaming_compatible_with_scalable_vectors(<vscale
258258

259259
declare <vscale x 2 x double> @normal_callee_scalable_vec_arg(<vscale x 2 x double>)
260260

261-
define <vscale x 2 x i1> @streaming_compatible_with_predicate_vectors(<vscale x 2 x i1> %arg) "aarch64_pstate_sm_compatible" nounwind #0 {
261+
define <vscale x 2 x i1> @streaming_compatible_with_predicate_vectors(<vscale x 2 x i1> %arg) "aarch64_pstate_sm_compatible" nounwind {
262262
; CHECK-LABEL: streaming_compatible_with_predicate_vectors:
263263
; CHECK: // %bb.0:
264264
; CHECK-NEXT: str x29, [sp, #-32]! // 8-byte Folded Spill
@@ -436,6 +436,3 @@ define void @disable_tailcallopt() "aarch64_pstate_sm_compatible" nounwind {
436436
tail call void @normal_callee();
437437
ret void;
438438
}
439-
440-
441-
attributes #0 = { nounwind "target-features"="+sve" }

‎llvm/test/CodeGen/AArch64/sme-streaming-interface.ll

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -147,7 +147,7 @@ define <4 x i32> @smstart_clobber_simdfp(<4 x i32> %x) nounwind {
147147
}
148148

149149
; Ensure SVE registers are preserved correctly.
150-
define <vscale x 4 x i32> @smstart_clobber_sve(<vscale x 4 x i32> %x) #0 {
150+
define <vscale x 4 x i32> @smstart_clobber_sve(<vscale x 4 x i32> %x) nounwind {
151151
; CHECK-LABEL: smstart_clobber_sve:
152152
; CHECK: // %bb.0:
153153
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
@@ -224,7 +224,7 @@ define <vscale x 4 x i32> @smstart_clobber_sve(<vscale x 4 x i32> %x) #0 {
224224

225225
; Call streaming callee twice; there should be no spills/fills between the two
226226
; calls since the registers should have already been clobbered.
227-
define <vscale x 4 x i32> @smstart_clobber_sve_duplicate(<vscale x 4 x i32> %x) #0 {
227+
define <vscale x 4 x i32> @smstart_clobber_sve_duplicate(<vscale x 4 x i32> %x) nounwind {
228228
; CHECK-LABEL: smstart_clobber_sve_duplicate:
229229
; CHECK: // %bb.0:
230230
; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
@@ -359,7 +359,7 @@ define void @disable_tailcallopt() nounwind {
359359
ret void;
360360
}
361361

362-
define i8 @call_to_non_streaming_pass_sve_objects(ptr nocapture noundef readnone %ptr) #1 {
362+
define i8 @call_to_non_streaming_pass_sve_objects(ptr nocapture noundef readnone %ptr) #0 {
363363
; CHECK-LABEL: call_to_non_streaming_pass_sve_objects:
364364
; CHECK: // %bb.0: // %entry
365365
; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
@@ -404,5 +404,4 @@ declare i64 @llvm.aarch64.sme.cntsb()
404404

405405
declare void @foo(ptr noundef, ptr noundef, ptr noundef, i64 noundef)
406406

407-
attributes #0 = { nounwind "target-features"="+sve" }
408-
attributes #1 = { nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" }
407+
attributes #0 = { nounwind vscale_range(1,16) "aarch64_pstate_sm_enabled" }

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-qcvtn.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py$
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2,+bf16 -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+bf16 -verify-machineinstrs < %s | FileCheck %s
33

44
;
55
; SQCVTN

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-and-combine.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3+
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
34

45
target triple = "aarch64-unknown-linux-gnu"
56

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bit-counting.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3+
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
34

45
target triple = "aarch64-unknown-linux-gnu"
56

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3+
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
34

45
target triple = "aarch64-unknown-linux-gnu"
56

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitselect.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3+
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
34

45
target triple = "aarch64"
56

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3+
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
34

45
target triple = "aarch64-unknown-linux-gnu"
56

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-concat.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3+
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
34

45
target triple = "aarch64-unknown-linux-gnu"
56

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ext-loads.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
3+
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
34

45
target triple = "aarch64-unknown-linux-gnu"
56

‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-subvector.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE
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; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-arith.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-convert.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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‎llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
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; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
56

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