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lukel97lukel97
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Address review comments
- Peek through copies to match isel better, remove most of test diff - Use liveins list to check for clobbers across blocks - Move messages into asserts - Add test for inline asm use - Assert no subregster index
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+1571
-1421
lines changed

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -605,7 +605,7 @@ void RISCVPassConfig::addPreRegAlloc() {
605605
// TODO: Move this as late as possible before regalloc
606606
if (TM->getOptLevel() == CodeGenOptLevel::None)
607607
addPass(createRISCVVMV0EliminationPass());
608-
608+
609609
addPass(createRISCVPreRAExpandPseudoPass());
610610
if (TM->getOptLevel() != CodeGenOptLevel::None) {
611611
addPass(createRISCVMergeBaseOffsetOptPass());

‎llvm/lib/Target/RISCV/RISCVVMV0Elimination.cpp

Lines changed: 34 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -72,6 +72,10 @@ FunctionPass *llvm::createRISCVVMV0EliminationPass() {
7272
return new RISCVVMV0Elimination();
7373
}
7474

75+
static bool isVMV0(const MCOperandInfo &MCOI) {
76+
return MCOI.RegClass == RISCV::VMV0RegClassID;
77+
}
78+
7579
bool RISCVVMV0Elimination::runOnMachineFunction(MachineFunction &MF) {
7680
if (skipFunction(MF.getFunction()))
7781
return false;
@@ -85,29 +89,26 @@ bool RISCVVMV0Elimination::runOnMachineFunction(MachineFunction &MF) {
8589
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
8690
const TargetInstrInfo *TII = ST->getInstrInfo();
8791

88-
auto IsVMV0 = [](const MCOperandInfo &MCOI) {
89-
return MCOI.RegClass == RISCV::VMV0RegClassID;
90-
};
91-
9292
#ifndef NDEBUG
93-
// Assert that we won't clobber any existing reads of V0 where we need to
93+
// Assert that we won't clobber any existing reads of v0 where we need to
9494
// insert copies.
9595
ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
96-
SmallPtrSet<MachineBasicBlock *, 8> V0ClobberedOnEntry;
9796
for (MachineBasicBlock *MBB : RPOT) {
98-
bool V0Clobbered = V0ClobberedOnEntry.contains(MBB);
97+
bool V0Clobbered = false;
9998
for (MachineInstr &MI : *MBB) {
100-
assert(!(MI.readsRegister(RISCV::V0, TRI) && V0Clobbered));
99+
assert(!(MI.readsRegister(RISCV::V0, TRI) && V0Clobbered) &&
100+
"Inserting a copy to v0 would clobber a read");
101101
if (MI.modifiesRegister(RISCV::V0, TRI))
102102
V0Clobbered = false;
103103

104-
if (any_of(MI.getDesc().operands(), IsVMV0))
104+
if (any_of(MI.getDesc().operands(), isVMV0))
105105
V0Clobbered = true;
106106
}
107107

108-
if (V0Clobbered)
109-
for (MachineBasicBlock *Succ : MBB->successors())
110-
V0ClobberedOnEntry.insert(Succ);
108+
assert(!(V0Clobbered &&
109+
any_of(MBB->successors(),
110+
[](auto *Succ) { return Succ->isLiveIn(RISCV::V0); })) &&
111+
"Clobbered a v0 used in a successor");
111112
}
112113
#endif
113114

@@ -116,14 +117,26 @@ bool RISCVVMV0Elimination::runOnMachineFunction(MachineFunction &MF) {
116117
// For any instruction with a vmv0 operand, replace it with a copy to v0.
117118
for (MachineBasicBlock &MBB : MF) {
118119
for (MachineInstr &MI : MBB) {
119-
// An instruction should only have one or zero vmv0 operands.
120-
assert(count_if(MI.getDesc().operands(), IsVMV0) < 2);
120+
assert(count_if(MI.getDesc().operands(), isVMV0) < 2 &&
121+
"Expected only one or zero vmv0 operands");
121122

122123
for (auto [OpNo, MCOI] : enumerate(MI.getDesc().operands())) {
123-
if (IsVMV0(MCOI)) {
124+
if (isVMV0(MCOI)) {
124125
MachineOperand &MO = MI.getOperand(OpNo);
126+
Register Src = MO.getReg();
127+
assert(MO.isUse() && MO.getSubReg() == RISCV::NoSubRegister &&
128+
Src.isVirtual() && "vmv0 use in unexpected form");
129+
130+
// Peek through a single copy to match what isel does.
131+
MachineInstr *SrcMI = MRI.getVRegDef(Src);
132+
if (SrcMI->isCopy() && SrcMI->getOperand(1).getReg().isVirtual()) {
133+
assert(SrcMI->getOperand(1).getSubReg() == RISCV::NoSubRegister);
134+
Src = SrcMI->getOperand(1).getReg();
135+
}
136+
125137
BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::COPY), RISCV::V0)
126-
.addReg(MO.getReg());
138+
.addReg(Src);
139+
127140
MO.setReg(RISCV::V0);
128141
MadeChange = true;
129142
break;
@@ -132,6 +145,9 @@ bool RISCVVMV0Elimination::runOnMachineFunction(MachineFunction &MF) {
132145
}
133146
}
134147

148+
if (!MadeChange)
149+
return false;
150+
135151
// Now that any constraints requiring vmv0 are gone, eliminate any uses of
136152
// vmv0 by recomputing the reg class.
137153
// The only remaining uses should be around inline asm.
@@ -143,7 +159,8 @@ bool RISCVVMV0Elimination::runOnMachineFunction(MachineFunction &MF) {
143159
MRI.recomputeRegClass(MO.getReg());
144160
assert(MRI.getRegClass(MO.getReg()) != &RISCV::VMV0RegClass ||
145161
MI.isInlineAsm() ||
146-
MRI.getVRegDef(MO.getReg())->isInlineAsm());
162+
MRI.getVRegDef(MO.getReg())->isInlineAsm() &&
163+
"Non-inline-asm use of vmv0 left behind");
147164
MadeChange = true;
148165
}
149166
}

‎llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -3065,27 +3065,27 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
30653065
; CHECK-NEXT: add a1, sp, a1
30663066
; CHECK-NEXT: addi a1, a1, 16
30673067
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
3068-
; CHECK-NEXT: csrr a4, vlenb
3068+
; CHECK-NEXT: csrr a3, vlenb
30693069
; CHECK-NEXT: lui a1, 1
30703070
; CHECK-NEXT: lui a2, 3
3071-
; CHECK-NEXT: srli a3, a4, 1
3072-
; CHECK-NEXT: slli a4, a4, 2
3073-
; CHECK-NEXT: vslidedown.vx v0, v0, a3
3074-
; CHECK-NEXT: sub a3, a0, a4
3075-
; CHECK-NEXT: sltu a5, a0, a3
3071+
; CHECK-NEXT: srli a4, a3, 1
3072+
; CHECK-NEXT: slli a3, a3, 2
3073+
; CHECK-NEXT: vslidedown.vx v0, v0, a4
3074+
; CHECK-NEXT: sub a4, a0, a3
3075+
; CHECK-NEXT: sltu a5, a0, a4
30763076
; CHECK-NEXT: addi a5, a5, -1
3077-
; CHECK-NEXT: and a5, a5, a3
3077+
; CHECK-NEXT: and a5, a5, a4
30783078
; CHECK-NEXT: lui a6, 5
3079-
; CHECK-NEXT: addi a3, a1, -241
3079+
; CHECK-NEXT: addi a4, a1, -241
30803080
; CHECK-NEXT: addi a2, a2, 819
30813081
; CHECK-NEXT: addi a1, a6, 1365
30823082
; CHECK-NEXT: vsetvli zero, a5, e16, m8, ta, ma
30833083
; CHECK-NEXT: vsrl.vi v8, v16, 8, v0.t
30843084
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
30853085
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
30863086
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
3087-
; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
3088-
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
3087+
; CHECK-NEXT: vand.vx v16, v16, a4, v0.t
3088+
; CHECK-NEXT: vand.vx v8, v8, a4, v0.t
30893089
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
30903090
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
30913091
; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t
@@ -3100,23 +3100,23 @@ define <vscale x 64 x i16> @vp_bitreverse_nxv64i16(<vscale x 64 x i16> %va, <vsc
31003100
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
31013101
; CHECK-NEXT: addi a5, sp, 16
31023102
; CHECK-NEXT: vs8r.v v8, (a5) # Unknown-size Folded Spill
3103-
; CHECK-NEXT: bltu a0, a4, .LBB46_2
3103+
; CHECK-NEXT: bltu a0, a3, .LBB46_2
31043104
; CHECK-NEXT: # %bb.1:
3105-
; CHECK-NEXT: mv a0, a4
3105+
; CHECK-NEXT: mv a0, a3
31063106
; CHECK-NEXT: .LBB46_2:
31073107
; CHECK-NEXT: vmv1r.v v0, v24
3108-
; CHECK-NEXT: csrr a4, vlenb
3109-
; CHECK-NEXT: slli a4, a4, 3
3110-
; CHECK-NEXT: add a4, sp, a4
3111-
; CHECK-NEXT: addi a4, a4, 16
3112-
; CHECK-NEXT: vl8r.v v16, (a4) # Unknown-size Folded Reload
3108+
; CHECK-NEXT: csrr a3, vlenb
3109+
; CHECK-NEXT: slli a3, a3, 3
3110+
; CHECK-NEXT: add a3, sp, a3
3111+
; CHECK-NEXT: addi a3, a3, 16
3112+
; CHECK-NEXT: vl8r.v v8, (a3) # Unknown-size Folded Reload
31133113
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
3114-
; CHECK-NEXT: vsrl.vi v8, v16, 8, v0.t
3115-
; CHECK-NEXT: vsll.vi v16, v16, 8, v0.t
3116-
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
3114+
; CHECK-NEXT: vsrl.vi v16, v8, 8, v0.t
3115+
; CHECK-NEXT: vsll.vi v8, v8, 8, v0.t
3116+
; CHECK-NEXT: vor.vv v8, v8, v16, v0.t
31173117
; CHECK-NEXT: vsrl.vi v16, v8, 4, v0.t
3118-
; CHECK-NEXT: vand.vx v16, v16, a3, v0.t
3119-
; CHECK-NEXT: vand.vx v8, v8, a3, v0.t
3118+
; CHECK-NEXT: vand.vx v16, v16, a4, v0.t
3119+
; CHECK-NEXT: vand.vx v8, v8, a4, v0.t
31203120
; CHECK-NEXT: vsll.vi v8, v8, 4, v0.t
31213121
; CHECK-NEXT: vor.vv v8, v16, v8, v0.t
31223122
; CHECK-NEXT: vsrl.vi v16, v8, 2, v0.t

‎llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll

Lines changed: 20 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -1498,66 +1498,59 @@ define <vscale x 16 x double> @vp_ceil_vv_nxv16f64(<vscale x 16 x double> %va, <
14981498
; CHECK-NEXT: addi sp, sp, -16
14991499
; CHECK-NEXT: .cfi_def_cfa_offset 16
15001500
; CHECK-NEXT: csrr a1, vlenb
1501-
; CHECK-NEXT: slli a1, a1, 4
1501+
; CHECK-NEXT: slli a1, a1, 3
15021502
; CHECK-NEXT: sub sp, sp, a1
1503-
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
1503+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
15041504
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
1505-
; CHECK-NEXT: vmv1r.v v24, v0
1506-
; CHECK-NEXT: addi a1, sp, 16
1507-
; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
1505+
; CHECK-NEXT: vmv1r.v v7, v0
15081506
; CHECK-NEXT: csrr a1, vlenb
15091507
; CHECK-NEXT: lui a2, %hi(.LCPI44_0)
15101508
; CHECK-NEXT: srli a3, a1, 3
15111509
; CHECK-NEXT: fld fa5, %lo(.LCPI44_0)(a2)
15121510
; CHECK-NEXT: sub a2, a0, a1
1513-
; CHECK-NEXT: vslidedown.vx v25, v0, a3
1511+
; CHECK-NEXT: vslidedown.vx v6, v0, a3
15141512
; CHECK-NEXT: sltu a3, a0, a2
15151513
; CHECK-NEXT: addi a3, a3, -1
15161514
; CHECK-NEXT: and a2, a3, a2
1517-
; CHECK-NEXT: vmv1r.v v0, v25
1515+
; CHECK-NEXT: vmv1r.v v0, v6
15181516
; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma
1519-
; CHECK-NEXT: vfabs.v v8, v16, v0.t
1517+
; CHECK-NEXT: vfabs.v v24, v16, v0.t
15201518
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
1521-
; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t
1519+
; CHECK-NEXT: vmflt.vf v6, v24, fa5, v0.t
15221520
; CHECK-NEXT: fsrmi a2, 3
1523-
; CHECK-NEXT: vmv1r.v v0, v25
1521+
; CHECK-NEXT: vmv1r.v v0, v6
15241522
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
1525-
; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t
1523+
; CHECK-NEXT: vfcvt.x.f.v v24, v16, v0.t
1524+
; CHECK-NEXT: addi a3, sp, 16
1525+
; CHECK-NEXT: vs8r.v v24, (a3) # Unknown-size Folded Spill
15261526
; CHECK-NEXT: fsrm a2
1527-
; CHECK-NEXT: vfcvt.f.x.v v8, v8, v0.t
1527+
; CHECK-NEXT: addi a2, sp, 16
1528+
; CHECK-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload
1529+
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t
15281530
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
1529-
; CHECK-NEXT: vfsgnj.vv v16, v8, v16, v0.t
1530-
; CHECK-NEXT: csrr a2, vlenb
1531-
; CHECK-NEXT: slli a2, a2, 3
1532-
; CHECK-NEXT: add a2, sp, a2
1533-
; CHECK-NEXT: addi a2, a2, 16
1531+
; CHECK-NEXT: vfsgnj.vv v16, v24, v16, v0.t
15341532
; CHECK-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
15351533
; CHECK-NEXT: bltu a0, a1, .LBB44_2
15361534
; CHECK-NEXT: # %bb.1:
15371535
; CHECK-NEXT: mv a0, a1
15381536
; CHECK-NEXT: .LBB44_2:
1539-
; CHECK-NEXT: vmv1r.v v0, v24
1540-
; CHECK-NEXT: addi a1, sp, 16
1541-
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
1537+
; CHECK-NEXT: vmv1r.v v0, v7
15421538
; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma
15431539
; CHECK-NEXT: vfabs.v v16, v8, v0.t
15441540
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
1545-
; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t
1541+
; CHECK-NEXT: vmflt.vf v7, v16, fa5, v0.t
15461542
; CHECK-NEXT: fsrmi a0, 3
1547-
; CHECK-NEXT: vmv1r.v v0, v24
1543+
; CHECK-NEXT: vmv1r.v v0, v7
15481544
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
15491545
; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
15501546
; CHECK-NEXT: fsrm a0
15511547
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
15521548
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu
15531549
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
1554-
; CHECK-NEXT: csrr a0, vlenb
1555-
; CHECK-NEXT: slli a0, a0, 3
1556-
; CHECK-NEXT: add a0, sp, a0
1557-
; CHECK-NEXT: addi a0, a0, 16
1550+
; CHECK-NEXT: addi a0, sp, 16
15581551
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
15591552
; CHECK-NEXT: csrr a0, vlenb
1560-
; CHECK-NEXT: slli a0, a0, 4
1553+
; CHECK-NEXT: slli a0, a0, 3
15611554
; CHECK-NEXT: add sp, sp, a0
15621555
; CHECK-NEXT: .cfi_def_cfa sp, 16
15631556
; CHECK-NEXT: addi sp, sp, 16

‎llvm/test/CodeGen/RISCV/rvv/copyprop.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,8 +45,8 @@ body: |
4545
%3:vr = COPY $v8
4646
%17:vr = PseudoVSLL_VI_M1 undef $noreg, %3, 5, 1, 6 /* e64 */, 0
4747
%22:vr = PseudoVMSNE_VI_M1 %3, 0, 1, 6 /* e64 */
48-
$v0 = COPY %22
49-
%25:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, %17, -1, $v0, 1, 6 /* e64 */
48+
%23:vmv0 = COPY %22
49+
%25:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, %17, -1, %23, 1, 6 /* e64 */
5050
%29:vr = PseudoVC_V_X_SE_M1 3, 31, %2, 1, 6 /* e64 */, implicit-def dead $sf_vcix_state, implicit $sf_vcix_state
5151
%30:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 1, 6 /* e64 */, 0
5252
BGEU %1, $x0, %bb.2

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