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1 parent 32cf55a commit b95ad8eCopy full SHA for b95ad8e
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9482,8 +9482,8 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
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// split into legal sized loads. This enables us to combine i64 load by i8
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// patterns to a couple of i32 loads on 32 bit targets.
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if (LegalOperations &&
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- !TLI.isOperationLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD,
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- MemVT))
+ !TLI.isLoadExtLegal(NeedsZext ? ISD::ZEXTLOAD : ISD::NON_EXTLOAD, VT,
+ MemVT))
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return SDValue();
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// Check if the bytes of the OR we are looking at match with either big or
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