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[SDAG] Handle insert_subvector in isKnownNeverNaN (#131989)
Propagate nnan across insert_subvector.
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‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5752,6 +5752,34 @@ bool SelectionDAG::isKnownNeverNaN(SDValue Op, const APInt &DemandedElts,
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}
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return isKnownNeverNaN(Src, SNaN, Depth + 1);
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}
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case ISD::INSERT_SUBVECTOR: {
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SDValue BaseVector = Op.getOperand(0);
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SDValue SubVector = Op.getOperand(1);
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EVT BaseVectorVT = BaseVector.getValueType();
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if (BaseVectorVT.isFixedLengthVector()) {
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unsigned Idx = Op.getConstantOperandVal(2);
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unsigned NumBaseElts = BaseVectorVT.getVectorNumElements();
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unsigned NumSubElts = SubVector.getValueType().getVectorNumElements();
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// Clear/Extract the bits at the position where the subvector will be
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// inserted.
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APInt DemandedMask =
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APInt::getBitsSet(NumBaseElts, Idx, Idx + NumSubElts);
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APInt DemandedSrcElts = DemandedElts & ~DemandedMask;
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APInt DemandedSubElts = DemandedElts.extractBits(NumSubElts, Idx);
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bool NeverNaN = true;
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if (!DemandedSrcElts.isZero())
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NeverNaN &=
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isKnownNeverNaN(BaseVector, DemandedSrcElts, SNaN, Depth + 1);
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if (NeverNaN && !DemandedSubElts.isZero())
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NeverNaN &=
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isKnownNeverNaN(SubVector, DemandedSubElts, SNaN, Depth + 1);
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return NeverNaN;
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}
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return isKnownNeverNaN(BaseVector, SNaN, Depth + 1) &&
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isKnownNeverNaN(SubVector, SNaN, Depth + 1);
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}
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case ISD::BUILD_VECTOR: {
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unsigned NumElts = Op.getNumOperands();
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for (unsigned I = 0; I != NumElts; ++I)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmaximum.ll

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,3 +357,52 @@ define <2 x half> @vfmax_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
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%v = call <2 x half> @llvm.maximum.v2f16(<2 x half> %a, <2 x half> %c)
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ret <2 x half> %v
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}
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declare <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half>, <2 x half>, i64)
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define <4 x half> @vfmax_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half> %b, <4 x half> %c) {
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; ZVFH-LABEL: vfmax_v2f16_vv_nnan_insert_subvector:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFH-NEXT: vfadd.vv v8, v8, v8
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; ZVFH-NEXT: vfadd.vv v9, v9, v9
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vmfeq.vv v0, v10, v10
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; ZVFH-NEXT: vslideup.vi v8, v9, 2
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; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
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; ZVFH-NEXT: vfmax.vv v8, v8, v10
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfmax_v2f16_vv_nnan_insert_subvector:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11
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; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9
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; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
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; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
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; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
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; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
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; ZVFHMIN-NEXT: vfmax.vv v9, v8, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%d = fadd nnan <2 x half> %a, %a
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%e = fadd nnan <2 x half> %b, %b
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%f = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> undef, <2 x half> %d, i64 0)
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%g = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> %f, <2 x half> %e, i64 2)
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%v = call <4 x half> @llvm.maximum.v4f16(<4 x half> %g, <4 x half> %c)
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ret <4 x half> %v
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}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fminimum.ll

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -357,3 +357,52 @@ define <2 x half> @vfmin_v2f16_vv_nnanb(<2 x half> %a, <2 x half> %b) {
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%v = call <2 x half> @llvm.minimum.v2f16(<2 x half> %a, <2 x half> %c)
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ret <2 x half> %v
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}
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declare <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half>, <2 x half>, i64)
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define <4 x half> @vfmin_v2f16_vv_nnan_insert_subvector(<2 x half> %a, <2 x half> %b, <4 x half> %c) {
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; ZVFH-LABEL: vfmin_v2f16_vv_nnan_insert_subvector:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFH-NEXT: vfadd.vv v8, v8, v8
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; ZVFH-NEXT: vfadd.vv v9, v9, v9
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; ZVFH-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFH-NEXT: vmfeq.vv v0, v10, v10
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; ZVFH-NEXT: vslideup.vi v8, v9, 2
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; ZVFH-NEXT: vmerge.vvm v8, v10, v8, v0
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; ZVFH-NEXT: vfmin.vv v8, v8, v10
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: vfmin_v2f16_vv_nnan_insert_subvector:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v11, v8
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v9
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
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; ZVFHMIN-NEXT: vfadd.vv v9, v11, v11
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; ZVFHMIN-NEXT: vfadd.vv v8, v8, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v11, v9
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; ZVFHMIN-NEXT: vfncvt.f.f.w v9, v8
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; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vslideup.vi v11, v9, 2
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v8, v11
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vmfeq.vv v0, v8, v8
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma
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; ZVFHMIN-NEXT: vmerge.vvm v10, v8, v9, v0
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; ZVFHMIN-NEXT: vmfeq.vv v0, v9, v9
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; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
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; ZVFHMIN-NEXT: vfmin.vv v9, v8, v10
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; ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vfncvt.f.f.w v8, v9
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; ZVFHMIN-NEXT: ret
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%d = fadd nnan <2 x half> %a, %a
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%e = fadd nnan <2 x half> %b, %b
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%f = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> undef, <2 x half> %d, i64 0)
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%g = call <4 x half> @llvm.vector.insert.v2f32.v4f32(<4 x half> %f, <2 x half> %e, i64 2)
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%v = call <4 x half> @llvm.minimum.v4f16(<4 x half> %g, <4 x half> %c)
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ret <4 x half> %v
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}

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