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IsWriteAfterRead -> IsReadAfterWrite and avoid using ops vector
1 parent 8a295fd commit b9616cb

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2 files changed

+8
-9
lines changed

2 files changed

+8
-9
lines changed

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1780,13 +1780,13 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
17801780
SDValue SinkValue = N->getOperand(1);
17811781
SDValue EltSize = N->getOperand(2);
17821782

1783-
bool IsWriteAfterRead =
1784-
N->getOpcode() == ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK;
1783+
bool IsReadAfterWrite =
1784+
N->getOpcode() == ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK;
17851785
auto VT = N->getValueType(0);
17861786
auto PtrVT = SourceValue->getValueType(0);
17871787

17881788
SDValue Diff = DAG.getNode(ISD::SUB, DL, PtrVT, SinkValue, SourceValue);
1789-
if (!IsWriteAfterRead)
1789+
if (IsReadAfterWrite)
17901790
Diff = DAG.getNode(ISD::ABS, DL, PtrVT, Diff);
17911791

17921792
Diff = DAG.getNode(ISD::SDIV, DL, PtrVT, Diff, EltSize);
@@ -1796,7 +1796,7 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
17961796
Diff.getValueType());
17971797
SDValue Zero = DAG.getTargetConstant(0, DL, PtrVT);
17981798
SDValue Cmp = DAG.getSetCC(DL, CmpVT, Diff, Zero,
1799-
IsWriteAfterRead ? ISD::SETLE : ISD::SETEQ);
1799+
IsReadAfterWrite ? ISD::SETEQ : ISD::SETLE);
18001800

18011801
// Create the lane mask
18021802
EVT SplatTY =
@@ -1807,7 +1807,7 @@ SDValue VectorLegalizer::ExpandLOOP_DEPENDENCE_MASK(SDNode *N) {
18071807
DAG.getSetCC(DL, VT, VectorStep, DiffSplat, ISD::CondCode::SETULT);
18081808

18091809
// Splat the compare result then OR it with the lane mask
1810-
auto VTElementTy = VT.getVectorElementType();
1810+
EVT VTElementTy = VT.getVectorElementType();
18111811
if (CmpVT.getScalarSizeInBits() < VTElementTy.getScalarSizeInBits())
18121812
Cmp = DAG.getNode(ISD::ZERO_EXTEND, DL, VTElementTy, Cmp);
18131813
SDValue Splat = DAG.getSplat(VT, DL, Cmp);

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8248,13 +8248,12 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I,
82488248
case Intrinsic::experimental_loop_dependence_raw_mask: {
82498249
auto IntrinsicVT = EVT::getEVT(I.getType());
82508250
SmallVector<SDValue, 4> Ops;
8251-
for (auto &Op : I.operands())
8252-
Ops.push_back(getValue(Op));
82538251
unsigned ID = Intrinsic == Intrinsic::experimental_loop_dependence_war_mask
82548252
? ISD::EXPERIMENTAL_LOOP_DEPENDENCE_WAR_MASK
82558253
: ISD::EXPERIMENTAL_LOOP_DEPENDENCE_RAW_MASK;
8256-
SDValue Mask = DAG.getNode(ID, sdl, IntrinsicVT, Ops);
8257-
setValue(&I, Mask);
8254+
setValue(&I,
8255+
DAG.getNode(ID, sdl, IntrinsicVT, getValue(I.getOperand(0)),
8256+
getValue(I.getOperand(1)), getValue(I.getOperand(2))));
82588257
}
82598258
}
82608259
}

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