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[RISCVISel] Compute leading zeros for RISCVISD::VCPOP_VL node (#127705)
This patch adds handling of the RISCVISD::VCPOP_VL node in RISCVTargetLowering::computeKnownBitsForTargetNode. It eliminates redundant zero-extension instructions.
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -19462,6 +19462,11 @@ void RISCVTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
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Known = Known.intersectWith(Known2);
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break;
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}
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case RISCVISD::VCPOP_VL: {
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KnownBits Known2 = DAG.computeKnownBits(Op.getOperand(2), Depth + 1);
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Known.Zero.setBitsFrom(Known2.countMaxActiveBits());
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break;
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}
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case RISCVISD::CZERO_EQZ:
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case RISCVISD::CZERO_NEZ:
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Known = DAG.computeKnownBits(Op.getOperand(0), Depth + 1);

‎llvm/test/CodeGen/RISCV/rvv/vcpop-compute-known-bits.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s --check-prefixes=CHECK,RV64
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define i32 @test(<8 x i1> %mask) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
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; CHECK-NEXT: vcpop.m a0, v0
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; CHECK-NEXT: ret
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%1 = bitcast <8 x i1> %mask to i8
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%2 = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 %1)
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%3 = zext nneg i8 %2 to i32
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ret i32 %3
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32: {{.*}}
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; RV64: {{.*}}

‎llvm/test/CodeGen/RISCV/rvv/vcpop-shl-zext-opt.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s --check-prefixes=CHECK,RV64
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define dso_local void @test_store1(ptr nocapture noundef writeonly %dst, ptr nocapture noundef readonly %src, i32 noundef signext %c, i32 noundef signext %n) {
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; RV32-LABEL: test_store1:
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; RV32: # %bb.0: # %entry
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; RV32-NEXT: blez a3, .LBB0_6
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; RV32-NEXT: # %bb.1: # %for.body.preheader
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; RV32-NEXT: li a4, 8
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; RV32-NEXT: bltu a3, a4, .LBB0_7
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; RV32-NEXT: # %bb.2: # %for.body.preheader
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; RV32-NEXT: sub a4, a0, a1
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; RV32-NEXT: sltu a5, a0, a1
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; RV32-NEXT: neg a5, a5
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; RV32-NEXT: sltiu a4, a4, 32
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; RV32-NEXT: seqz a5, a5
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; RV32-NEXT: and a4, a5, a4
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; RV32-NEXT: bnez a4, .LBB0_7
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; RV32-NEXT: # %bb.3: # %vector.ph
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; RV32-NEXT: lui a5, 524288
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; RV32-NEXT: addi a5, a5, -8
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; RV32-NEXT: and a5, a3, a5
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; RV32-NEXT: li a7, 0
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; RV32-NEXT: li a6, 0
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; RV32-NEXT: .LBB0_4: # %vector.body
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: slli t0, a7, 2
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; RV32-NEXT: addi t1, a7, 8
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; RV32-NEXT: add t0, a1, t0
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; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; RV32-NEXT: vle32.v v8, (t0)
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; RV32-NEXT: sltu a7, t1, a7
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; RV32-NEXT: xor t0, t1, a5
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; RV32-NEXT: add a6, a6, a7
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; RV32-NEXT: vmslt.vx v10, v8, a2
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; RV32-NEXT: vcompress.vm v12, v8, v10
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; RV32-NEXT: vcpop.m a7, v10
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; RV32-NEXT: vsetvli zero, a7, e32, m2, ta, ma
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; RV32-NEXT: vse32.v v12, (a0)
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; RV32-NEXT: slli a7, a7, 2
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; RV32-NEXT: or t0, t0, a6
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; RV32-NEXT: add a0, a0, a7
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; RV32-NEXT: mv a7, t1
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; RV32-NEXT: bnez t0, .LBB0_4
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; RV32-NEXT: # %bb.5: # %middle.block
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; RV32-NEXT: bne a5, a3, .LBB0_9
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; RV32-NEXT: .LBB0_6: # %for.cond.cleanup
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; RV32-NEXT: ret
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; RV32-NEXT: .LBB0_7:
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; RV32-NEXT: li a5, 0
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; RV32-NEXT: li a4, 0
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; RV32-NEXT: j .LBB0_9
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; RV32-NEXT: .LBB0_8: # %for.inc
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; RV32-NEXT: # in Loop: Header=BB0_9 Depth=1
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; RV32-NEXT: addi a5, a5, 1
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; RV32-NEXT: seqz a6, a5
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; RV32-NEXT: add a4, a4, a6
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; RV32-NEXT: xor a6, a5, a3
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; RV32-NEXT: or a6, a6, a4
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; RV32-NEXT: beqz a6, .LBB0_6
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; RV32-NEXT: .LBB0_9: # %for.body
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; RV32-NEXT: # =>This Inner Loop Header: Depth=1
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; RV32-NEXT: slli a6, a5, 2
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; RV32-NEXT: add a6, a1, a6
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; RV32-NEXT: lw a6, 0(a6)
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; RV32-NEXT: bge a6, a2, .LBB0_8
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; RV32-NEXT: # %bb.10: # %if.then
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; RV32-NEXT: # in Loop: Header=BB0_9 Depth=1
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; RV32-NEXT: addi a7, a0, 4
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; RV32-NEXT: sw a6, 0(a0)
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; RV32-NEXT: mv a0, a7
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; RV32-NEXT: j .LBB0_8
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;
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; RV64-LABEL: test_store1:
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; RV64: # %bb.0: # %entry
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; RV64-NEXT: blez a3, .LBB0_6
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; RV64-NEXT: # %bb.1: # %for.body.preheader
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; RV64-NEXT: li a5, 8
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; RV64-NEXT: li a4, 0
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; RV64-NEXT: bltu a3, a5, .LBB0_7
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; RV64-NEXT: # %bb.2: # %for.body.preheader
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; RV64-NEXT: sub a5, a0, a1
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; RV64-NEXT: li a6, 31
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; RV64-NEXT: bgeu a6, a5, .LBB0_7
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; RV64-NEXT: # %bb.3: # %vector.ph
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; RV64-NEXT: lui a4, 524288
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; RV64-NEXT: addiw a4, a4, -8
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; RV64-NEXT: and a4, a3, a4
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; RV64-NEXT: slli a5, a4, 2
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; RV64-NEXT: add a5, a5, a1
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; RV64-NEXT: mv a6, a1
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; RV64-NEXT: .LBB0_4: # %vector.body
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; RV64-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; RV64-NEXT: vle32.v v8, (a6)
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; RV64-NEXT: addi a6, a6, 32
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; RV64-NEXT: vmslt.vx v10, v8, a2
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; RV64-NEXT: vcompress.vm v12, v8, v10
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; RV64-NEXT: vcpop.m a7, v10
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; RV64-NEXT: vsetvli zero, a7, e32, m2, ta, ma
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; RV64-NEXT: vse32.v v12, (a0)
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; RV64-NEXT: slli a7, a7, 2
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; RV64-NEXT: add a0, a0, a7
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; RV64-NEXT: bne a6, a5, .LBB0_4
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; RV64-NEXT: # %bb.5: # %middle.block
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; RV64-NEXT: bne a4, a3, .LBB0_7
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; RV64-NEXT: .LBB0_6: # %for.cond.cleanup
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; RV64-NEXT: ret
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; RV64-NEXT: .LBB0_7: # %for.body.preheader13
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; RV64-NEXT: slli a4, a4, 2
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; RV64-NEXT: slli a5, a3, 2
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; RV64-NEXT: add a3, a1, a4
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; RV64-NEXT: add a1, a1, a5
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; RV64-NEXT: j .LBB0_9
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; RV64-NEXT: .LBB0_8: # %for.inc
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; RV64-NEXT: # in Loop: Header=BB0_9 Depth=1
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; RV64-NEXT: addi a3, a3, 4
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; RV64-NEXT: beq a3, a1, .LBB0_6
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; RV64-NEXT: .LBB0_9: # %for.body
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; RV64-NEXT: # =>This Inner Loop Header: Depth=1
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; RV64-NEXT: lw a4, 0(a3)
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; RV64-NEXT: bge a4, a2, .LBB0_8
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; RV64-NEXT: # %bb.10: # %if.then
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; RV64-NEXT: # in Loop: Header=BB0_9 Depth=1
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; RV64-NEXT: addi a5, a0, 4
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; RV64-NEXT: sw a4, 0(a0)
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; RV64-NEXT: mv a0, a5
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; RV64-NEXT: j .LBB0_8
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entry:
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%cmp8 = icmp sgt i32 %n, 0
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br i1 %cmp8, label %for.body.preheader, label %for.cond.cleanup
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for.body.preheader: ; preds = %entry
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%dst11 = ptrtoint ptr %dst to i64
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%src12 = ptrtoint ptr %src to i64
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%wide.trip.count = zext nneg i32 %n to i64
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%min.iters.check = icmp ult i32 %n, 8
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%0 = sub i64 %dst11, %src12
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%diff.check = icmp ult i64 %0, 32
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%or.cond = or i1 %min.iters.check, %diff.check
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br i1 %or.cond, label %for.body.preheader13, label %vector.ph
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for.body.preheader13: ; preds = %middle.block, %for.body.preheader
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%indvars.iv.ph = phi i64 [ 0, %for.body.preheader ], [ %n.vec, %middle.block ]
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%dst.addr.09.ph = phi ptr [ %dst, %for.body.preheader ], [ %monotonic.add, %middle.block ]
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br label %for.body
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vector.ph: ; preds = %for.body.preheader
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%n.vec = and i64 %wide.trip.count, 2147483640
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%broadcast.splatinsert = insertelement <8 x i32> poison, i32 %c, i64 0
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%broadcast.splat = shufflevector <8 x i32> %broadcast.splatinsert, <8 x i32> poison, <8 x i32> zeroinitializer
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i64 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%monotonic.iv = phi ptr [ %dst, %vector.ph ], [ %monotonic.add, %vector.body ]
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%1 = getelementptr inbounds i32, ptr %src, i64 %index
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%wide.load = load <8 x i32>, ptr %1, align 4
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%2 = icmp slt <8 x i32> %wide.load, %broadcast.splat
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tail call void @llvm.masked.compressstore.v8i32(<8 x i32> %wide.load, ptr align 4 %monotonic.iv, <8 x i1> %2)
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%3 = bitcast <8 x i1> %2 to i8
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%4 = tail call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 %3)
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%5 = shl nuw nsw i8 %4, 2
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%6 = zext nneg i8 %5 to i64
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%monotonic.add = getelementptr inbounds i8, ptr %monotonic.iv, i64 %6
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%index.next = add nuw i64 %index, 8
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%7 = icmp eq i64 %index.next, %n.vec
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br i1 %7, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i64 %n.vec, %wide.trip.count
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br i1 %cmp.n, label %for.cond.cleanup, label %for.body.preheader13
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for.cond.cleanup: ; preds = %for.inc, %middle.block, %entry
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ret void
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for.body: ; preds = %for.body.preheader13, %for.inc
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ %indvars.iv.ph, %for.body.preheader13 ]
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%dst.addr.09 = phi ptr [ %dst.addr.1, %for.inc ], [ %dst.addr.09.ph, %for.body.preheader13 ]
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%arrayidx = getelementptr inbounds i32, ptr %src, i64 %indvars.iv
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%8 = load i32, ptr %arrayidx, align 4
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%cmp1 = icmp slt i32 %8, %c
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br i1 %cmp1, label %if.then, label %for.inc
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if.then: ; preds = %for.body
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%incdec.ptr = getelementptr inbounds i8, ptr %dst.addr.09, i64 4
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store i32 %8, ptr %dst.addr.09, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%dst.addr.1 = phi ptr [ %incdec.ptr, %if.then ], [ %dst.addr.09, %for.body ]
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %wide.trip.count
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK: {{.*}}

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