[AMDGPU] Don't S_MOV_B32 into $scc

The peephole optimizer tries to replace
```
%n:sgpr_32 = S_MOV_B32 x
$scc = COPY %n
```
with a `S_MOV_B32` directly into `$scc`.

This crashes because `S_MOV_B32` cannot take `$scc` as input.

We currently generate code like this from GlobalISel when lowering a
G_BRCOND with a constant condition. We should probably look into
removing this kind of branch altogether, but until then we should at
least not crash.

This patch fixes the issue by making sure we don't apply the peephole
optimization when trying to move into a physical register that
doesn't belong to the correct register class.

Differential Revision: https://reviews.llvm.org/D148117

Author: rovka

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -3090,7 +3090,12 @@ bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
       assert(UseMI.getOperand(1).getReg().isVirtual());
     }
 
-    UseMI.setDesc(get(NewOpc));
+    const MCInstrDesc &NewMCID = get(NewOpc);
+    if (DstReg.isPhysical() &&
+        !RI.getRegClass(NewMCID.operands()[0].RegClass)->contains(DstReg))
+      return false;
+
+    UseMI.setDesc(NewMCID);
     UseMI.getOperand(1).ChangeToImmediate(Imm.getSExtValue());
     UseMI.addImplicitDefUseOperands(*UseMI.getParent()->getParent());
     return true;

llvm/test/CodeGen/AMDGPU/fold_16bit_imm.mir renamed to llvm/test/CodeGen/AMDGPU/peephole-fold-imm.mir

@@ -1,6 +1,51 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs -run-pass peephole-opt -o - %s | FileCheck -check-prefix=GCN %s
 
+---
+name:            fold_simm_virtual
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: fold_simm_virtual
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: SI_RETURN_TO_EPILOG
+    %0:sreg_32 = S_MOV_B32 0
+    %1:sreg_32 = COPY killed %0
+    SI_RETURN_TO_EPILOG
+
+...
+
+---
+name:            fold_simm_physical
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: fold_simm_physical
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: $sgpr1 = S_MOV_B32 0
+    ; GCN-NEXT: SI_RETURN_TO_EPILOG
+    %0:sreg_32 = S_MOV_B32 0
+    $sgpr1 = COPY killed %0
+    SI_RETURN_TO_EPILOG
+
+...
+
+---
+name:            dont_fold_simm_scc
+body:             |
+  bb.0:
+
+    ; GCN-LABEL: name: dont_fold_simm_scc
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
+    ; GCN-NEXT: $scc = COPY killed [[S_MOV_B32_]]
+    ; GCN-NEXT: SI_RETURN_TO_EPILOG
+    %0:sreg_32 = S_MOV_B32 0
+    $scc = COPY killed %0
+    SI_RETURN_TO_EPILOG
+
+...
+
 ---
 name:            fold_simm_16_sub_to_lo
 body:             |