Skip to content

Commit b9d7aa7

Browse files
LiqinWengLiqinWeng
committed
[LV][VPlan] set FastMathFlags on EVLRecipe
Currently support: 1. vp.fpext/vp.fptrunc of VPWidenCastRecipe 2. vp.select of VPWidenSelectRecipe 3. vp.select of VPInstruction
1 parent deb1fd8 commit b9d7aa7

10 files changed

+38
-23
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1652,8 +1652,8 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
16521652

16531653
VPWidenIntrinsicRecipe(Intrinsic::ID VectorIntrinsicID,
16541654
ArrayRef<VPValue *> CallArguments, Type *Ty,
1655-
DebugLoc DL = {})
1656-
: VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments, DL),
1655+
FastMathFlags FMFs, DebugLoc DL = {})
1656+
: VPRecipeWithIRFlags(VPDef::VPWidenIntrinsicSC, CallArguments, FMFs, DL),
16571657
VectorIntrinsicID(VectorIntrinsicID), ResultTy(Ty) {
16581658
LLVMContext &Ctx = Ty->getContext();
16591659
AttributeList Attrs = Intrinsic::getAttributes(Ctx, VectorIntrinsicID);
@@ -1667,9 +1667,10 @@ class VPWidenIntrinsicRecipe : public VPRecipeWithIRFlags {
16671667

16681668
VPWidenIntrinsicRecipe(Intrinsic::ID VectorIntrinsicID,
16691669
std::initializer_list<VPValue *> CallArguments,
1670-
Type *Ty, DebugLoc DL = {})
1670+
Type *Ty, FastMathFlags FMFs, DebugLoc DL = {})
16711671
: VPWidenIntrinsicRecipe(VectorIntrinsicID,
1672-
ArrayRef<VPValue *>(CallArguments), Ty, DL) {}
1672+
ArrayRef<VPValue *>(CallArguments), Ty, FMFs,
1673+
DL) {}
16731674

16741675
~VPWidenIntrinsicRecipe() override = default;
16751676

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,8 +1062,11 @@ void VPWidenIntrinsicRecipe::execute(VPTransformState &State) {
10621062
CI->getOperandBundlesAsDefs(OpBundles);
10631063

10641064
CallInst *V = State.Builder.CreateCall(VectorF, Args, OpBundles);
1065-
1066-
setFlags(V);
1065+
// vector-predication intrinsics only accept FMF flags, while vector intrinsic
1066+
// can support all flags.
1067+
bool VPIntrinsic = VPIntrinsic::isVPIntrinsic(VectorIntrinsicID);
1068+
if ((VPIntrinsic && isa<FPMathOperator>(V)) || !VPIntrinsic)
1069+
setFlags(V);
10671070

10681071
if (!V->getType()->isVoidTy())
10691072
State.set(this, V);

‎llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp

Lines changed: 15 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1565,17 +1565,24 @@ static VPRecipeBase *createEVLRecipe(VPValue *HeaderMask,
15651565
VPIntrinsic::getVectorLengthParamPos(VPID) &&
15661566
"Expected VP intrinsic to have mask and EVL");
15671567

1568+
FastMathFlags FMFs = {};
1569+
if (CR->hasFastMathFlags())
1570+
FMFs = CR->getFastMathFlags();
15681571
SmallVector<VPValue *> Ops(CR->operands());
15691572
Ops.push_back(&AllOneMask);
15701573
Ops.push_back(&EVL);
1571-
return new VPWidenIntrinsicRecipe(
1572-
VPID, Ops, TypeInfo.inferScalarType(CR), CR->getDebugLoc());
1574+
return new VPWidenIntrinsicRecipe(VPID, Ops,
1575+
TypeInfo.inferScalarType(CR),
1576+
FMFs, CR->getDebugLoc());
15731577
})
15741578
.Case<VPWidenSelectRecipe>([&](VPWidenSelectRecipe *Sel) {
1579+
FastMathFlags FMFs = {};
1580+
if (Sel->hasFastMathFlags())
1581+
FMFs = Sel->getFastMathFlags();
15751582
SmallVector<VPValue *> Ops(Sel->operands());
15761583
Ops.push_back(&EVL);
15771584
return new VPWidenIntrinsicRecipe(Intrinsic::vp_select, Ops,
1578-
TypeInfo.inferScalarType(Sel),
1585+
TypeInfo.inferScalarType(Sel), FMFs,
15791586
Sel->getDebugLoc());
15801587
})
15811588
.Case<VPInstruction>([&](VPInstruction *VPI) -> VPRecipeBase * {
@@ -1587,11 +1594,15 @@ static VPRecipeBase *createEVLRecipe(VPValue *HeaderMask,
15871594
if (!match(VPI, m_Select(m_Specific(HeaderMask), m_VPValue(LHS),
15881595
m_VPValue(RHS))))
15891596
return nullptr;
1597+
1598+
FastMathFlags FMFs = {};
1599+
if (VPI->hasFastMathFlags())
1600+
FMFs = VPI->getFastMathFlags();
15901601
// Use all true as the condition because this transformation is
15911602
// limited to selects whose condition is a header mask.
15921603
return new VPWidenIntrinsicRecipe(
15931604
Intrinsic::vp_merge, {&AllOneMask, LHS, RHS, &EVL},
1594-
TypeInfo.inferScalarType(LHS), VPI->getDebugLoc());
1605+
TypeInfo.inferScalarType(LHS), FMFs, VPI->getDebugLoc());
15951606
})
15961607
.Default([&](VPRecipeBase *R) { return nullptr; });
15971608
}

‎llvm/test/Transforms/LoopVectorize/RISCV/inloop-reduction.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -662,7 +662,7 @@ define nofpclass(nan inf) float @vp_reduction_with_fastflags(ptr %a, ptr %b, i6
662662
; IF-EVL-OUTLOOP-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 0
663663
; IF-EVL-OUTLOOP-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
664664
; IF-EVL-OUTLOOP-NEXT: [[VP_OP:%.*]] = call fast <vscale x 4 x float> @llvm.vp.fadd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
665-
; IF-EVL-OUTLOOP-NEXT: [[TMP14]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
665+
; IF-EVL-OUTLOOP-NEXT: [[TMP14]] = call fast <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
666666
; IF-EVL-OUTLOOP-NEXT: [[TMP15:%.*]] = zext i32 [[TMP10]] to i64
667667
; IF-EVL-OUTLOOP-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP15]], [[EVL_BASED_IV]]
668668
; IF-EVL-OUTLOOP-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-cast-intrinsics.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -447,7 +447,7 @@ define void @vp_fpext_with_fastflags(ptr %a, ptr %b, i64 %N) {
447447
; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP13]]
448448
; IF-EVL-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 0
449449
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x float> @llvm.vp.load.nxv2f32.p0(ptr align 4 [[TMP15]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META30:![0-9]+]]
450-
; IF-EVL-NEXT: [[TMP16:%.*]] = call <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f32(<vscale x 2 x float> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
450+
; IF-EVL-NEXT: [[TMP16:%.*]] = call fast <vscale x 2 x double> @llvm.vp.fpext.nxv2f64.nxv2f32(<vscale x 2 x float> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
451451
; IF-EVL-NEXT: [[TMP17:%.*]] = getelementptr inbounds double, ptr [[A]], i64 [[TMP13]]
452452
; IF-EVL-NEXT: [[TMP18:%.*]] = getelementptr inbounds double, ptr [[TMP17]], i32 0
453453
; IF-EVL-NEXT: call void @llvm.vp.store.nxv2f64.p0(<vscale x 2 x double> [[TMP16]], ptr align 8 [[TMP18]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META33:![0-9]+]], !noalias [[META30]]
@@ -647,7 +647,7 @@ define void @vp_fptrunc_with_fastflags(ptr %a, ptr %b, i64 %N) {
647647
; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds double, ptr [[B]], i64 [[TMP13]]
648648
; IF-EVL-NEXT: [[TMP15:%.*]] = getelementptr inbounds double, ptr [[TMP14]], i32 0
649649
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 2 x double> @llvm.vp.load.nxv2f64.p0(ptr align 8 [[TMP15]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META44:![0-9]+]]
650-
; IF-EVL-NEXT: [[TMP16:%.*]] = call <vscale x 2 x float> @llvm.vp.fptrunc.nxv2f32.nxv2f64(<vscale x 2 x double> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
650+
; IF-EVL-NEXT: [[TMP16:%.*]] = call fast <vscale x 2 x float> @llvm.vp.fptrunc.nxv2f32.nxv2f64(<vscale x 2 x double> [[VP_OP_LOAD]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]])
651651
; IF-EVL-NEXT: [[TMP17:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP13]]
652652
; IF-EVL-NEXT: [[TMP18:%.*]] = getelementptr inbounds float, ptr [[TMP17]], i32 0
653653
; IF-EVL-NEXT: call void @llvm.vp.store.nxv2f32.p0(<vscale x 2 x float> [[TMP16]], ptr align 4 [[TMP18]], <vscale x 2 x i1> splat (i1 true), i32 [[TMP12]]), !alias.scope [[META47:![0-9]+]], !noalias [[META44]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reduction.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1108,7 +1108,7 @@ define float @fadd(ptr %a, i64 %n, float %start) {
11081108
; IF-EVL-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[TMP12]], i32 0
11091109
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP13]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
11101110
; IF-EVL-NEXT: [[VP_OP:%.*]] = call reassoc <vscale x 4 x float> @llvm.vp.fadd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1111-
; IF-EVL-NEXT: [[TMP14]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
1111+
; IF-EVL-NEXT: [[TMP14]] = call reassoc <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
11121112
; IF-EVL-NEXT: [[TMP15:%.*]] = zext i32 [[TMP10]] to i64
11131113
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP15]], [[EVL_BASED_IV]]
11141114
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
@@ -1311,7 +1311,7 @@ define float @fmin(ptr %a, i64 %n, float %start) #0 {
13111311
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
13121312
; IF-EVL-NEXT: [[TMP13:%.*]] = fcmp fast olt <vscale x 4 x float> [[VP_OP_LOAD]], [[VEC_PHI]]
13131313
; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP13]], <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1314-
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1314+
; IF-EVL-NEXT: [[TMP15]] = call fast <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
13151315
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
13161316
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
13171317
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
@@ -1438,7 +1438,7 @@ define float @fmax(ptr %a, i64 %n, float %start) #0 {
14381438
; IF-EVL-NEXT: [[VP_OP_LOAD:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP12]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP9]])
14391439
; IF-EVL-NEXT: [[TMP13:%.*]] = fcmp fast ogt <vscale x 4 x float> [[VP_OP_LOAD]], [[VEC_PHI]]
14401440
; IF-EVL-NEXT: [[TMP14:%.*]] = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP13]], <vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1441-
; IF-EVL-NEXT: [[TMP15]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
1441+
; IF-EVL-NEXT: [[TMP15]] = call fast <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP14]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP9]])
14421442
; IF-EVL-NEXT: [[TMP16:%.*]] = zext i32 [[TMP9]] to i64
14431443
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP16]], [[EVL_BASED_IV]]
14441444
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]
@@ -1727,8 +1727,8 @@ define float @fmuladd(ptr %a, ptr %b, i64 %n, float %start) {
17271727
; IF-EVL-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[B:%.*]], i64 [[TMP11]]
17281728
; IF-EVL-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 0
17291729
; IF-EVL-NEXT: [[VP_OP_LOAD1:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP15]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1730-
; IF-EVL-NEXT: [[TMP16:%.*]] = call <vscale x 4 x float> @llvm.vp.fmuladd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VP_OP_LOAD1]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1731-
; IF-EVL-NEXT: [[TMP17]] = call <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP16]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
1730+
; IF-EVL-NEXT: [[TMP16:%.*]] = call reassoc <vscale x 4 x float> @llvm.vp.fmuladd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> [[VP_OP_LOAD1]], <vscale x 4 x float> [[VEC_PHI]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP10]])
1731+
; IF-EVL-NEXT: [[TMP17]] = call reassoc <vscale x 4 x float> @llvm.vp.merge.nxv4f32(<vscale x 4 x i1> splat (i1 true), <vscale x 4 x float> [[TMP16]], <vscale x 4 x float> [[VEC_PHI]], i32 [[TMP10]])
17321732
; IF-EVL-NEXT: [[TMP18:%.*]] = zext i32 [[TMP10]] to i64
17331733
; IF-EVL-NEXT: [[INDEX_EVL_NEXT]] = add i64 [[TMP18]], [[EVL_BASED_IV]]
17341734
; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP8]]

‎llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-select-intrinsics.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -183,7 +183,7 @@ define void @vp_select_with_fastflags(ptr %a, ptr %b, ptr %c, i64 %N) {
183183
; IF-EVL-NEXT: [[VP_OP_LOAD5:%.*]] = call <vscale x 4 x float> @llvm.vp.load.nxv4f32.p0(ptr align 4 [[TMP21]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])
184184
; IF-EVL-NEXT: [[TMP22:%.*]] = fcmp fast ogt <vscale x 4 x float> [[VP_OP_LOAD]], [[VP_OP_LOAD5]]
185185
; IF-EVL-NEXT: [[VP_OP:%.*]] = call fast <vscale x 4 x float> @llvm.vp.fadd.nxv4f32(<vscale x 4 x float> [[VP_OP_LOAD]], <vscale x 4 x float> splat (float 1.000000e+01), <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])
186-
; IF-EVL-NEXT: [[TMP23:%.*]] = call <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP22]], <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VP_OP_LOAD5]], i32 [[TMP16]])
186+
; IF-EVL-NEXT: [[TMP23:%.*]] = call fast <vscale x 4 x float> @llvm.vp.select.nxv4f32(<vscale x 4 x i1> [[TMP22]], <vscale x 4 x float> [[VP_OP]], <vscale x 4 x float> [[VP_OP_LOAD5]], i32 [[TMP16]])
187187
; IF-EVL-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP17]]
188188
; IF-EVL-NEXT: [[TMP25:%.*]] = getelementptr inbounds float, ptr [[TMP24]], i32 0
189189
; IF-EVL-NEXT: call void @llvm.vp.store.nxv4f32.p0(<vscale x 4 x float> [[TMP23]], ptr align 4 [[TMP25]], <vscale x 4 x i1> splat (i1 true), i32 [[TMP16]])

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-cast-intrinsics.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -217,7 +217,7 @@ define void @vp_fpext_with_fastfalgs(ptr %a, ptr %b, i64 %N) {
217217
; IF-EVL-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%b>, vp<[[ST]]>
218218
; IF-EVL-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
219219
; IF-EVL-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
220-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPEXT:%.+]]> = call llvm.vp.fpext(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
220+
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPEXT:%.+]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.fpext(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
221221
; IF-EVL-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
222222
; IF-EVL-NEXT: vp<[[PTR2:%[0-9]+]]> = vector-pointer ir<[[GEP2]]>
223223
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR2]]>, vp<[[FPEXT]]>, vp<[[EVL]]>
@@ -313,7 +313,7 @@ define void @vp_fptrunc_with_fastflags(ptr %a, ptr %b, i64 %N) {
313313
; IF-EVL-NEXT: CLONE ir<[[GEP1:%.+]]> = getelementptr inbounds ir<%b>, vp<[[ST]]>
314314
; IF-EVL-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
315315
; IF-EVL-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
316-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPTRUNC:%.+]]> = call llvm.vp.fptrunc(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
316+
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[FPTRUNC:%.+]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.fptrunc(ir<[[LD1]]>, ir<true>, vp<[[EVL]]>)
317317
; IF-EVL-NEXT: CLONE ir<[[GEP2:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
318318
; IF-EVL-NEXT: vp<[[PTR2:%[0-9]+]]> = vector-pointer ir<[[GEP2]]>
319319
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR2]]>, vp<[[FPTRUNC]]>, vp<[[EVL]]>

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-intrinsics-reduction.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -261,7 +261,7 @@ define nofpclass(nan inf) float @vp_reduction_with_fastflags(ptr %a, ptr %b, i64
261261
; IF-EVL-OUTLOOP-NEXT: vp<[[PTR1:%[0-9]+]]> = vector-pointer ir<[[GEP1]]>
262262
; IF-EVL-OUTLOOP-NEXT: WIDEN ir<[[LD1:%.+]]> = vp.load vp<[[PTR1]]>, vp<[[EVL]]>
263263
; IF-EVL-OUTLOOP-NEXT: WIDEN ir<[[FADD:%.+]]> = vp.fadd reassoc nnan ninf nsz arcp contract afn ir<[[LD1]]>, ir<[[RDX_PHI]]>, vp<[[EVL]]>
264-
; IF-EVL-OUTLOOP-NEXT: WIDEN-INTRINSIC vp<[[RDX_SELECT]]> = call llvm.vp.merge(ir<true>, ir<[[FADD]]>, ir<[[RDX_PHI]]>, vp<[[EVL]]>)
264+
; IF-EVL-OUTLOOP-NEXT: WIDEN-INTRINSIC vp<[[RDX_SELECT]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.merge(ir<true>, ir<[[FADD]]>, ir<[[RDX_PHI]]>, vp<[[EVL]]>)
265265
; IF-EVL-OUTLOOP-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
266266
; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[IV_NEXT]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
267267
; IF-EVL-OUTLOOP-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add vp<[[IV]]>, vp<[[VFUF]]>

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ define void @vp_select_with_fastflags(ptr %a, ptr %b, ptr %c, i64 %N) {
8383
; IF-EVL-NEXT: WIDEN ir<[[LD2:%.+]]> = vp.load vp<[[PTR2]]>, vp<[[EVL]]>
8484
; IF-EVL-NEXT: WIDEN ir<[[FCMP:%.+]]> = fcmp ogt ir<[[LD1]]>, ir<[[LD2]]>
8585
; IF-EVL-NEXT: WIDEN ir<[[FADD:%.+]]> = vp.fadd reassoc nnan ninf nsz arcp contract afn ir<[[LD1]]>, ir<1.000000e+01>, vp<[[EVL]]>
86-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call llvm.vp.select(ir<[[FCMP]]>, ir<[[FADD]]>, ir<[[LD2]]>, vp<[[EVL]]>)
86+
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call reassoc nnan ninf nsz arcp contract afn llvm.vp.select(ir<[[FCMP]]>, ir<[[FADD]]>, ir<[[LD2]]>, vp<[[EVL]]>)
8787
; IF-EVL-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
8888
; IF-EVL-NEXT: vp<[[PTR3:%.+]]> = vector-pointer ir<[[GEP3]]>
8989
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR3]]>, vp<[[SELECT]]>, vp<[[EVL]]>

0 commit comments

Comments
 (0)