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Jessica Paquette
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[GlobalISel][AArch64] Legalize G_FNEARBYINT
Add legalizer support for G_FNEARBYINT. It's the same as G_FCEIL etc. Since the importer allows us to automatically select this after legalization, also add tests for selection etc. Also update arm64-vfloatintrinsics.ll. llvm-svn: 359204
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8 files changed

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-2
lines changed

8 files changed

+589
-2
lines changed

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1323,6 +1323,7 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
13231323
case TargetOpcode::G_FLOG:
13241324
case TargetOpcode::G_FLOG2:
13251325
case TargetOpcode::G_FRINT:
1326+
case TargetOpcode::G_FNEARBYINT:
13261327
case TargetOpcode::G_FSQRT:
13271328
case TargetOpcode::G_FEXP:
13281329
case TargetOpcode::G_FEXP2:
@@ -2191,6 +2192,7 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
21912192
case G_FLOG:
21922193
case G_FLOG2:
21932194
case G_FLOG10:
2195+
case G_FNEARBYINT:
21942196
case G_FCEIL:
21952197
case G_FFLOOR:
21962198
case G_FRINT:

‎llvm/lib/Target/AArch64/AArch64LegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -131,7 +131,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) {
131131
getActionDefinitionsBuilder(G_FREM).libcallFor({s32, s64});
132132

133133
getActionDefinitionsBuilder({G_FCEIL, G_FABS, G_FSQRT, G_FFLOOR, G_FRINT,
134-
G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND})
134+
G_FMA, G_INTRINSIC_TRUNC, G_INTRINSIC_ROUND,
135+
G_FNEARBYINT})
135136
// If we don't have full FP16 support, then scalarize the elements of
136137
// vectors containing fp16 types.
137138
.fewerElementsIf(

‎llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -396,6 +396,7 @@ static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
396396
case TargetOpcode::G_FPTRUNC:
397397
case TargetOpcode::G_FCEIL:
398398
case TargetOpcode::G_FFLOOR:
399+
case TargetOpcode::G_FNEARBYINT:
399400
case TargetOpcode::G_FNEG:
400401
case TargetOpcode::G_FCOS:
401402
case TargetOpcode::G_FSIN:

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-nearbyint.mir

Lines changed: 234 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,234 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=FP16
3+
# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=legalizer -mattr=-fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=NO-FP16
4+
5+
...
6+
---
7+
name: test_v4f16.nearbyint
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alignment: 2
9+
tracksRegLiveness: true
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machineFunctionInfo: {}
11+
body: |
12+
bb.0:
13+
liveins: $d0
14+
15+
; FP16-LABEL: name: test_v4f16.nearbyint
16+
; FP16: liveins: $d0
17+
; FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
18+
; FP16: [[FNEARBYINT:%[0-9]+]]:_(<4 x s16>) = G_FNEARBYINT [[COPY]]
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; FP16: $d0 = COPY [[FNEARBYINT]](<4 x s16>)
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; FP16: RET_ReallyLR implicit $d0
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; NO-FP16-LABEL: name: test_v4f16.nearbyint
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; NO-FP16: liveins: $d0
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; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
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; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
25+
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
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; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT]]
27+
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT]](s32)
28+
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
29+
; NO-FP16: [[FNEARBYINT1:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT1]]
30+
; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT1]](s32)
31+
; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
32+
; NO-FP16: [[FNEARBYINT2:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT2]]
33+
; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT2]](s32)
34+
; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
35+
; NO-FP16: [[FNEARBYINT3:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT3]]
36+
; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT3]](s32)
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; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
38+
; NO-FP16: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
39+
; NO-FP16: RET_ReallyLR implicit $d0
40+
%0:_(<4 x s16>) = COPY $d0
41+
%1:_(<4 x s16>) = G_FNEARBYINT %0
42+
$d0 = COPY %1(<4 x s16>)
43+
RET_ReallyLR implicit $d0
44+
45+
...
46+
---
47+
name: test_v8f16.nearbyint
48+
alignment: 2
49+
tracksRegLiveness: true
50+
machineFunctionInfo: {}
51+
body: |
52+
bb.0:
53+
liveins: $q0
54+
55+
; FP16-LABEL: name: test_v8f16.nearbyint
56+
; FP16: liveins: $q0
57+
; FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
58+
; FP16: [[FNEARBYINT:%[0-9]+]]:_(<8 x s16>) = G_FNEARBYINT [[COPY]]
59+
; FP16: $q0 = COPY [[FNEARBYINT]](<8 x s16>)
60+
; FP16: RET_ReallyLR implicit $q0
61+
; NO-FP16-LABEL: name: test_v8f16.nearbyint
62+
; NO-FP16: liveins: $q0
63+
; NO-FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
64+
; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
65+
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
66+
; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT]]
67+
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT]](s32)
68+
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
69+
; NO-FP16: [[FNEARBYINT1:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT1]]
70+
; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT1]](s32)
71+
; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
72+
; NO-FP16: [[FNEARBYINT2:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT2]]
73+
; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT2]](s32)
74+
; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
75+
; NO-FP16: [[FNEARBYINT3:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT3]]
76+
; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT3]](s32)
77+
; NO-FP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
78+
; NO-FP16: [[FNEARBYINT4:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT4]]
79+
; NO-FP16: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT4]](s32)
80+
; NO-FP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
81+
; NO-FP16: [[FNEARBYINT5:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT5]]
82+
; NO-FP16: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT5]](s32)
83+
; NO-FP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
84+
; NO-FP16: [[FNEARBYINT6:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT6]]
85+
; NO-FP16: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT6]](s32)
86+
; NO-FP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
87+
; NO-FP16: [[FNEARBYINT7:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT7]]
88+
; NO-FP16: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT7]](s32)
89+
; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
90+
; NO-FP16: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
91+
; NO-FP16: RET_ReallyLR implicit $q0
92+
%0:_(<8 x s16>) = COPY $q0
93+
%1:_(<8 x s16>) = G_FNEARBYINT %0
94+
$q0 = COPY %1(<8 x s16>)
95+
RET_ReallyLR implicit $q0
96+
97+
...
98+
---
99+
name: test_v2f32.nearbyint
100+
alignment: 2
101+
tracksRegLiveness: true
102+
machineFunctionInfo: {}
103+
body: |
104+
bb.0:
105+
liveins: $d0
106+
107+
; FP16-LABEL: name: test_v2f32.nearbyint
108+
; FP16: liveins: $d0
109+
; FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
110+
; FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s32>) = G_FNEARBYINT [[COPY]]
111+
; FP16: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
112+
; FP16: RET_ReallyLR implicit $d0
113+
; NO-FP16-LABEL: name: test_v2f32.nearbyint
114+
; NO-FP16: liveins: $d0
115+
; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
116+
; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s32>) = G_FNEARBYINT [[COPY]]
117+
; NO-FP16: $d0 = COPY [[FNEARBYINT]](<2 x s32>)
118+
; NO-FP16: RET_ReallyLR implicit $d0
119+
%0:_(<2 x s32>) = COPY $d0
120+
%1:_(<2 x s32>) = G_FNEARBYINT %0
121+
$d0 = COPY %1(<2 x s32>)
122+
RET_ReallyLR implicit $d0
123+
124+
...
125+
---
126+
name: test_v2f64.nearbyint
127+
alignment: 2
128+
tracksRegLiveness: true
129+
machineFunctionInfo: {}
130+
body: |
131+
bb.0:
132+
liveins: $q0
133+
134+
; FP16-LABEL: name: test_v2f64.nearbyint
135+
; FP16: liveins: $q0
136+
; FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
137+
; FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s64>) = G_FNEARBYINT [[COPY]]
138+
; FP16: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
139+
; FP16: RET_ReallyLR implicit $q0
140+
; NO-FP16-LABEL: name: test_v2f64.nearbyint
141+
; NO-FP16: liveins: $q0
142+
; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
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; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(<2 x s64>) = G_FNEARBYINT [[COPY]]
144+
; NO-FP16: $q0 = COPY [[FNEARBYINT]](<2 x s64>)
145+
; NO-FP16: RET_ReallyLR implicit $q0
146+
%0:_(<2 x s64>) = COPY $q0
147+
%1:_(<2 x s64>) = G_FNEARBYINT %0
148+
$q0 = COPY %1(<2 x s64>)
149+
RET_ReallyLR implicit $q0
150+
151+
...
152+
---
153+
name: test_f32.nearbyint
154+
alignment: 2
155+
tracksRegLiveness: true
156+
machineFunctionInfo: {}
157+
body: |
158+
bb.0:
159+
liveins: $s0
160+
161+
; FP16-LABEL: name: test_f32.nearbyint
162+
; FP16: liveins: $s0
163+
; FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
164+
; FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[COPY]]
165+
; FP16: $s0 = COPY [[FNEARBYINT]](s32)
166+
; FP16: RET_ReallyLR implicit $s0
167+
; NO-FP16-LABEL: name: test_f32.nearbyint
168+
; NO-FP16: liveins: $s0
169+
; NO-FP16: [[COPY:%[0-9]+]]:_(s32) = COPY $s0
170+
; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[COPY]]
171+
; NO-FP16: $s0 = COPY [[FNEARBYINT]](s32)
172+
; NO-FP16: RET_ReallyLR implicit $s0
173+
%0:_(s32) = COPY $s0
174+
%1:_(s32) = G_FNEARBYINT %0
175+
$s0 = COPY %1(s32)
176+
RET_ReallyLR implicit $s0
177+
178+
...
179+
---
180+
name: test_f64.nearbyint
181+
alignment: 2
182+
tracksRegLiveness: true
183+
machineFunctionInfo: {}
184+
body: |
185+
bb.0:
186+
liveins: $d0
187+
188+
; FP16-LABEL: name: test_f64.nearbyint
189+
; FP16: liveins: $d0
190+
; FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
191+
; FP16: [[FNEARBYINT:%[0-9]+]]:_(s64) = G_FNEARBYINT [[COPY]]
192+
; FP16: $d0 = COPY [[FNEARBYINT]](s64)
193+
; FP16: RET_ReallyLR implicit $d0
194+
; NO-FP16-LABEL: name: test_f64.nearbyint
195+
; NO-FP16: liveins: $d0
196+
; NO-FP16: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
197+
; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s64) = G_FNEARBYINT [[COPY]]
198+
; NO-FP16: $d0 = COPY [[FNEARBYINT]](s64)
199+
; NO-FP16: RET_ReallyLR implicit $d0
200+
%0:_(s64) = COPY $d0
201+
%1:_(s64) = G_FNEARBYINT %0
202+
$d0 = COPY %1(s64)
203+
RET_ReallyLR implicit $d0
204+
205+
...
206+
---
207+
name: test_f16.nearbyint
208+
alignment: 2
209+
tracksRegLiveness: true
210+
machineFunctionInfo: {}
211+
body: |
212+
bb.0:
213+
liveins: $h0
214+
215+
; FP16-LABEL: name: test_f16.nearbyint
216+
; FP16: liveins: $h0
217+
; FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
218+
; FP16: [[FNEARBYINT:%[0-9]+]]:_(s16) = G_FNEARBYINT [[COPY]]
219+
; FP16: $h0 = COPY [[FNEARBYINT]](s16)
220+
; FP16: RET_ReallyLR implicit $h0
221+
; NO-FP16-LABEL: name: test_f16.nearbyint
222+
; NO-FP16: liveins: $h0
223+
; NO-FP16: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
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; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[COPY]](s16)
225+
; NO-FP16: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FPEXT]]
226+
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FNEARBYINT]](s32)
227+
; NO-FP16: $h0 = COPY [[FPTRUNC]](s16)
228+
; NO-FP16: RET_ReallyLR implicit $h0
229+
%0:_(s16) = COPY $h0
230+
%1:_(s16) = G_FNEARBYINT %0
231+
$h0 = COPY %1(s16)
232+
RET_ReallyLR implicit $h0
233+
234+
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -352,7 +352,7 @@
352352
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
353353
#
354354
# DEBUG-NEXT: G_FNEARBYINT (opcode {{[0-9]+}}): 1 type index
355-
# DEBUG: .. type index coverage check SKIPPED: no rules defined
355+
# DEBUG: .. type index coverage check SKIPPED: user-defined predicate detected
356356

357357
# CHECK-NOT: ill-defined
358358

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