Skip to content

Commit ba8e424

Browse files
RKSimonRKSimon
authored
[X86] Add missing immediate qualifier to the (V)INSERTPS instruction names (#108568)
Matches (V)BLENDPS etc and makes it easier to algorithmically recreate the instruction name in various analysis scripts I'm working on
1 parent 86f0399 commit ba8e424

File tree

6 files changed

+35
-35
lines changed

6 files changed

+35
-35
lines changed

‎llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -703,14 +703,14 @@ bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
703703
DestName = getRegName(MI->getOperand(0).getReg());
704704
break;
705705

706-
case X86::INSERTPSrr:
707-
case X86::VINSERTPSrr:
708-
case X86::VINSERTPSZrr:
706+
case X86::INSERTPSrri:
707+
case X86::VINSERTPSrri:
708+
case X86::VINSERTPSZrri:
709709
Src2Name = getRegName(MI->getOperand(2).getReg());
710710
[[fallthrough]];
711-
case X86::INSERTPSrm:
712-
case X86::VINSERTPSrm:
713-
case X86::VINSERTPSZrm:
711+
case X86::INSERTPSrmi:
712+
case X86::VINSERTPSrmi:
713+
case X86::VINSERTPSZrmi:
714714
DestName = getRegName(MI->getOperand(0).getReg());
715715
Src1Name = getRegName(MI->getOperand(1).getReg());
716716
if (MI->getOperand(NumOperands - 1).isImm())

‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -649,12 +649,12 @@ defm : vinsert_for_mask_cast<"VINSERTI64x4Z", v32i8x_info, v64i8_info,
649649
// vinsertps - insert f32 to XMM
650650
let ExeDomain = SSEPackedSingle in {
651651
let isCommutable = 1 in
652-
def VINSERTPSZrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
652+
def VINSERTPSZrri : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
653653
(ins VR128X:$src1, VR128X:$src2, u8imm:$src3),
654654
"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
655655
[(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, timm:$src3))]>,
656656
EVEX, VVVV, Sched<[SchedWriteFShuffle.XMM]>;
657-
def VINSERTPSZrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
657+
def VINSERTPSZrmi : AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
658658
(ins VR128X:$src1, f32mem:$src2, u8imm:$src3),
659659
"vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
660660
[(set VR128X:$dst, (X86insertps VR128X:$src1,

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2424,9 +2424,9 @@ MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
24242424
WorkingMI->getOperand(3).setImm(Mask ^ Imm);
24252425
break;
24262426
}
2427-
case X86::INSERTPSrr:
2428-
case X86::VINSERTPSrr:
2429-
case X86::VINSERTPSZrr: {
2427+
case X86::INSERTPSrri:
2428+
case X86::VINSERTPSrri:
2429+
case X86::VINSERTPSZrri: {
24302430
unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
24312431
unsigned ZMask = Imm & 15;
24322432
unsigned DstIdx = (Imm >> 4) & 3;
@@ -7274,9 +7274,9 @@ MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
72747274
ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
72757275
unsigned Size, Align Alignment) const {
72767276
switch (MI.getOpcode()) {
7277-
case X86::INSERTPSrr:
7278-
case X86::VINSERTPSrr:
7279-
case X86::VINSERTPSZrr:
7277+
case X86::INSERTPSrri:
7278+
case X86::VINSERTPSrri:
7279+
case X86::VINSERTPSZrri:
72807280
// Attempt to convert the load of inserted vector into a fold load
72817281
// of a single float.
72827282
if (OpNum == 2) {
@@ -7289,13 +7289,13 @@ MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
72897289
const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
72907290
unsigned RCSize = TRI.getRegSizeInBits(*RC) / 8;
72917291
if ((Size == 0 || Size >= 16) && RCSize >= 16 &&
7292-
(MI.getOpcode() != X86::INSERTPSrr || Alignment >= Align(4))) {
7292+
(MI.getOpcode() != X86::INSERTPSrri || Alignment >= Align(4))) {
72937293
int PtrOffset = SrcIdx * 4;
72947294
unsigned NewImm = (DstIdx << 4) | ZMask;
72957295
unsigned NewOpCode =
7296-
(MI.getOpcode() == X86::VINSERTPSZrr) ? X86::VINSERTPSZrm
7297-
: (MI.getOpcode() == X86::VINSERTPSrr) ? X86::VINSERTPSrm
7298-
: X86::INSERTPSrm;
7296+
(MI.getOpcode() == X86::VINSERTPSZrri) ? X86::VINSERTPSZrmi
7297+
: (MI.getOpcode() == X86::VINSERTPSrri) ? X86::VINSERTPSrmi
7298+
: X86::INSERTPSrmi;
72997299
MachineInstr *NewMI =
73007300
fuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
73017301
NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);

‎llvm/lib/Target/X86/X86InstrSSE.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5447,7 +5447,7 @@ let Constraints = "$src1 = $dst" in
54475447
// in the target vector.
54485448
multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
54495449
let isCommutable = 1 in
5450-
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
5450+
def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
54515451
(ins VR128:$src1, VR128:$src2, u8imm:$src3),
54525452
!if(Is2Addr,
54535453
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
@@ -5456,7 +5456,7 @@ multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {
54565456
[(set VR128:$dst,
54575457
(X86insertps VR128:$src1, VR128:$src2, timm:$src3))]>,
54585458
Sched<[SchedWriteFShuffle.XMM]>;
5459-
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
5459+
def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
54605460
(ins VR128:$src1, f32mem:$src2, u8imm:$src3),
54615461
!if(Is2Addr,
54625462
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),

‎llvm/test/CodeGen/X86/evex-to-vex-compress.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2304,10 +2304,10 @@ body: |
23042304
VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm0, 1
23052305
; CHECK: $eax = VEXTRACTPSrr $xmm0, 1
23062306
$eax = VEXTRACTPSZrr $xmm0, 1
2307-
; CHECK: $xmm0 = VINSERTPSrm $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
2308-
$xmm0 = VINSERTPSZrm $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
2309-
; CHECK: $xmm0 = VINSERTPSrr $xmm0, $xmm0, 1
2310-
$xmm0 = VINSERTPSZrr $xmm0, $xmm0, 1
2307+
; CHECK: $xmm0 = VINSERTPSrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
2308+
$xmm0 = VINSERTPSZrmi $xmm0, $rdi, 1, $noreg, 0, $noreg, 1
2309+
; CHECK: $xmm0 = VINSERTPSrri $xmm0, $xmm0, 1
2310+
$xmm0 = VINSERTPSZrri $xmm0, $xmm0, 1
23112311
; CHECK: $xmm0 = VROUNDSDmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
23122312
$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
23132313
; CHECK: $xmm0 = VROUNDSDri $xmm0, $xmm1, 15, implicit $mxcsr
@@ -4072,10 +4072,10 @@ body: |
40724072
VEXTRACTPSZmr $rdi, 1, $noreg, 0, $noreg, $xmm16, 1
40734073
; CHECK: $eax = VEXTRACTPSZrr $xmm16, 1
40744074
$eax = VEXTRACTPSZrr $xmm16, 1
4075-
; CHECK: $xmm16 = VINSERTPSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
4076-
$xmm16 = VINSERTPSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
4077-
; CHECK: $xmm16 = VINSERTPSZrr $xmm16, $xmm16, 1
4078-
$xmm16 = VINSERTPSZrr $xmm16, $xmm16, 1
4075+
; CHECK: $xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
4076+
$xmm16 = VINSERTPSZrmi $xmm16, $rdi, 1, $noreg, 0, $noreg, 1
4077+
; CHECK: $xmm16 = VINSERTPSZrri $xmm16, $xmm16, 1
4078+
$xmm16 = VINSERTPSZrri $xmm16, $xmm16, 1
40794079
; CHECK: $xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
40804080
$xmm16 = VRNDSCALEPDZ128rmi $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
40814081
; CHECK: $xmm16 = VRNDSCALEPDZ128rri $xmm16, 15, implicit $mxcsr

‎llvm/utils/TableGen/X86ManualFoldTables.def

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -215,18 +215,18 @@ NOFOLD(UD1Wr)
215215
// Exclude these two b/c they would conflict with {MMX_MOVD64from64rr, MMX_MOVQ64mr} in unfolding table
216216
NOFOLD(MMX_MOVQ64rr)
217217
NOFOLD(MMX_MOVQ64rr_REV)
218-
// INSERTPSrm has no count_s while INSERTPSrr has count_s.
218+
// INSERTPSrmi has no count_s while INSERTPSrri has count_s.
219219
// count_s is to indicate which element in dst vector is inserted.
220-
// if count_s!=0, we can not fold INSERTPSrr into INSERTPSrm
220+
// if count_s!=0, we can not fold INSERTPSrri into INSERTPSrmi
221221
//
222222
// the following folding can happen when count_s==0
223223
// load xmm0, m32
224-
// insertpsrr xmm1, xmm0, imm
224+
// INSERTPSrri xmm1, xmm0, imm
225225
// =>
226-
// insertpsrm xmm1, m32, imm
227-
NOFOLD(INSERTPSrr)
228-
NOFOLD(VINSERTPSZrr)
229-
NOFOLD(VINSERTPSrr)
226+
// INSERTPSrmi xmm1, m32, imm
227+
NOFOLD(INSERTPSrri)
228+
NOFOLD(VINSERTPSZrri)
229+
NOFOLD(VINSERTPSrri)
230230
// Memory faults are suppressed for CFCMOV with memory operand.
231231
NOFOLD(CFCMOV16rr_REV)
232232
NOFOLD(CFCMOV32rr_REV)

0 commit comments

Comments
 (0)