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AMDGPU/GlobalISel: Legalize s16->s64 G_FPTOSI/G_FPTOUI
Add narrowScalarFor action. Add narrow scalar for typeIndex == 0 for G_FPTOSI/G_FPTOUI. Legalize using narrowScalarFor as s16->s32 G_FPTOSI/G_FPTOUI followed by s32->s64 G_SEXT/G_ZEXT. Differential Revision: https://reviews.llvm.org/D84010
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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h

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@@ -696,6 +696,13 @@ class LegalizeRuleSet {
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markAllIdxsAsCovered();
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return actionIf(LegalizeAction::NarrowScalar, Predicate, Mutation);
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}
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/// Narrow the scalar, specified in mutation, when type indexes 0 and 1 is any
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/// type pair in the given list.
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LegalizeRuleSet &
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narrowScalarFor(std::initializer_list<std::pair<LLT, LLT>> Types,
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LegalizeMutation Mutation) {
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return actionFor(LegalizeAction::NarrowScalar, Types, Mutation);
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}
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/// Add more elements to reach the type selected by the mutation if the
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/// predicate is true.

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

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@@ -1212,6 +1212,22 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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Observer.changedInstr(MI);
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return Legalized;
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}
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case TargetOpcode::G_FPTOUI: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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Observer.changingInstr(MI);
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narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
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Observer.changedInstr(MI);
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return Legalized;
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}
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case TargetOpcode::G_FPTOSI: {
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if (TypeIdx != 0)
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return UnableToLegalize;
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Observer.changingInstr(MI);
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narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_SEXT);
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Observer.changedInstr(MI);
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return Legalized;
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}
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}
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}
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‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 2 additions & 1 deletion
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@@ -654,7 +654,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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auto &FPToI = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalFor({{S32, S32}, {S32, S64}, {S32, S16}})
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.customFor({{S64, S64}});
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.customFor({{S64, S64}})
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.narrowScalarFor({{S64, S16}}, changeTo(0, S32));
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if (ST.has16BitInsts())
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FPToI.legalFor({{S16, S16}});
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else

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir

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@@ -587,3 +587,64 @@ body: |
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%1:_(<2 x s64>) = G_FPTOSI %0
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
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...
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---
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name: test_fptosi_s16_to_s64
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_fptosi_s16_to_s64
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
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; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
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; VI-LABEL: name: test_fptosi_s16_to_s64
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
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; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
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; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s64) = G_FPTOSI %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_fptosi_v2s16_to_v2s64
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_fptosi_v2s16_to_v2s64
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; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
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; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
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; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC1]](s16)
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; SI: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI1]](s32)
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; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
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; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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; VI-LABEL: name: test_fptosi_v2s16_to_v2s64
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; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
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; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI]](s32)
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; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC1]](s16)
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; VI: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI1]](s32)
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; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
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; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s64>) = G_FPTOSI %0
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -757,3 +757,64 @@ body: |
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%1:_(<2 x s64>) = G_FPTOUI %0
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
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...
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---
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name: test_fptoui_s16_to_s64
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_fptoui_s16_to_s64
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
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; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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; VI-LABEL: name: test_fptoui_s16_to_s64
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
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; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
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; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s64) = G_FPTOUI %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: test_fptoui_v2s16_to_v2s64
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_fptoui_v2s16_to_v2s64
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; SI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; SI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; SI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
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; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
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; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
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; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC1]](s16)
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; SI: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI1]](s32)
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; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
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; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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; VI-LABEL: name: test_fptoui_v2s16_to_v2s64
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; VI: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $vgpr0
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; VI: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>)
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; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[BITCAST]](s32)
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; VI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32)
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; VI: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32)
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; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC]](s16)
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; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI]](s32)
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; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC1]](s16)
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; VI: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI1]](s32)
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; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
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; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s16>) = COPY $vgpr0
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%1:_(<2 x s64>) = G_FPTOUI %0
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
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...

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