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[amdgpu] Fix a crash case when preserving MDT in SILowerControlFlow
- When a redundant MBB is being erased from MDT, check whether its single successor is dominiated by it. If yes, update that successor's idom before erasing MBB; otherwise, it implies MBB is a leaf node and could be erased directly. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D111831
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‎llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -768,8 +768,15 @@ bool SILowerControlFlow::removeMBBifRedundant(MachineBasicBlock &MBB) {
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for (auto &I : MBB.instrs())
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LIS->RemoveMachineInstrFromMaps(I);
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}
771-
if (MDT)
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if (MDT) {
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// If Succ, the single successor of MBB, is dominated by MBB, MDT needs
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// updating by changing Succ's idom to the one of MBB; otherwise, MBB must
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// be a leaf node in MDT and could be erased directly.
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if (MDT->dominates(&MBB, Succ))
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MDT->changeImmediateDominator(MDT->getNode(Succ),
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MDT->getNode(&MBB)->getIDom());
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MDT->eraseNode(&MBB);
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}
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MBB.clear();
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MBB.eraseFromParent();
775782
if (FallThrough && !FallThrough->isLayoutSuccessor(Succ)) {

‎llvm/test/CodeGen/AMDGPU/mdt-preserving-crash.ll

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
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; RUN: llc < %s
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
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target triple = "amdgcn-amd-amdhsa"
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@_RSENC_gDcd_______________________________ = external protected addrspace(1) externally_initialized global [4096 x i8], align 16
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define protected amdgpu_kernel void @_RSENC_PRInit__________________________________() local_unnamed_addr #0 {
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entry:
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%runtimeVersionCopy = alloca [128 x i8], align 16, addrspace(5)
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%licenseVersionCopy = alloca [128 x i8], align 16, addrspace(5)
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%pD10 = alloca [128 x i8], align 16, addrspace(5)
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br label %if.end
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if.end: ; preds = %entry
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%0 = load i32, i32* undef, align 4
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%mul = mul i32 %0, 3
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%cmp13 = icmp eq i32 %mul, 989619
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br i1 %cmp13, label %cleanup.cont, label %if.end15
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if.end15: ; preds = %if.end
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br i1 undef, label %cleanup.cont, label %lor.lhs.false17
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lor.lhs.false17: ; preds = %if.end15
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br label %while.cond.i
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while.cond.i: ; preds = %while.cond.i, %lor.lhs.false17
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switch i32 undef, label %if.end60 [
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i32 0, label %while.cond.i
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i32 3, label %if.end60.loopexit857
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]
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if.end60.loopexit857: ; preds = %while.cond.i
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br label %if.end60
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if.end60: ; preds = %if.end60.loopexit857, %while.cond.i
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%1 = load i8, i8 addrspace(1)* getelementptr inbounds ([4096 x i8], [4096 x i8] addrspace(1)* @_RSENC_gDcd_______________________________, i64 0, i64 655), align 1
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%2 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %runtimeVersionCopy, i32 0, i32 0
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%arrayidx144260.5 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %runtimeVersionCopy, i32 0, i32 5
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%3 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %licenseVersionCopy, i32 0, i32 0
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%arrayidx156258.5 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %licenseVersionCopy, i32 0, i32 5
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switch i8 0, label %if.end5.i [
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i8 45, label %if.then.i
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i8 43, label %if.then3.i
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]
45+
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if.then.i: ; preds = %if.end60
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unreachable
48+
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if.then3.i: ; preds = %if.end60
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br label %if.end5.i
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if.end5.i: ; preds = %if.then3.i, %if.end60
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%pS.addr.0.i = phi i8 addrspace(5)* [ undef, %if.then3.i ], [ %2, %if.end60 ]
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%4 = load i8, i8 addrspace(5)* %pS.addr.0.i, align 1
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%conv612.i = sext i8 %4 to i32
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%sub13.i = add nsw i32 %conv612.i, -48
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%cmp714.i = icmp ugt i32 %sub13.i, 9
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switch i8 undef, label %if.end5.i314 [
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i8 45, label %if.then.i306
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i8 43, label %if.then3.i308
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]
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if.then.i306: ; preds = %if.end5.i
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unreachable
65+
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if.then3.i308: ; preds = %if.end5.i
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br label %if.end5.i314
68+
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if.end5.i314: ; preds = %if.then3.i308, %if.end5.i
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%pS.addr.0.i309 = phi i8 addrspace(5)* [ undef, %if.then3.i308 ], [ %3, %if.end5.i ]
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%5 = load i8, i8 addrspace(5)* %pS.addr.0.i309, align 1
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%conv612.i311 = sext i8 %5 to i32
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%sub13.i312 = add nsw i32 %conv612.i311, -48
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%cmp714.i313 = icmp ugt i32 %sub13.i312, 9
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switch i8 undef, label %if.end5.i338 [
76+
i8 45, label %if.then.i330
77+
i8 43, label %if.then3.i332
78+
]
79+
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if.then.i330: ; preds = %if.end5.i314
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unreachable
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if.then3.i332: ; preds = %if.end5.i314
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br label %if.end5.i338
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if.end5.i338: ; preds = %if.then3.i332, %if.end5.i314
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%pS.addr.0.i333 = phi i8 addrspace(5)* [ undef, %if.then3.i332 ], [ %arrayidx144260.5, %if.end5.i314 ]
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%6 = load i8, i8 addrspace(5)* %pS.addr.0.i333, align 1
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%conv612.i335 = sext i8 %6 to i32
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%sub13.i336 = add nsw i32 %conv612.i335, -48
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%cmp714.i337 = icmp ugt i32 %sub13.i336, 9
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switch i8 undef, label %if.end5.i362 [
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i8 45, label %if.then.i354
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i8 43, label %if.then3.i356
95+
]
96+
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if.then.i354: ; preds = %if.end5.i338
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unreachable
99+
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if.then3.i356: ; preds = %if.end5.i338
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br label %if.end5.i362
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if.end5.i362: ; preds = %if.then3.i356, %if.end5.i338
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%pS.addr.0.i357 = phi i8 addrspace(5)* [ undef, %if.then3.i356 ], [ %arrayidx156258.5, %if.end5.i338 ]
105+
%7 = load i8, i8 addrspace(5)* %pS.addr.0.i357, align 1
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%conv612.i359 = sext i8 %7 to i32
107+
%sub13.i360 = add nsw i32 %conv612.i359, -48
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%cmp714.i361 = icmp ugt i32 %sub13.i360, 9
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store i8 0, i8 addrspace(5)* undef, align 16
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%8 = load i8, i8 addrspace(1)* getelementptr inbounds ([4096 x i8], [4096 x i8] addrspace(1)* @_RSENC_gDcd_______________________________, i64 0, i64 1153), align 1
111+
%arrayidx232250.1 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %pD10, i32 0, i32 1
112+
store i8 %8, i8 addrspace(5)* %arrayidx232250.1, align 1
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switch i8 undef, label %if.end5.i400 [
114+
i8 45, label %if.then.i392
115+
i8 43, label %if.then3.i394
116+
]
117+
118+
if.then.i392: ; preds = %if.end5.i362
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unreachable
120+
121+
if.then3.i394: ; preds = %if.end5.i362
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br label %if.end5.i400
123+
124+
if.end5.i400: ; preds = %if.then3.i394, %if.end5.i362
125+
%pS.addr.0.i395 = phi i8 addrspace(5)* [ %arrayidx232250.1, %if.then3.i394 ], [ undef, %if.end5.i362 ]
126+
%9 = load i8, i8 addrspace(5)* %pS.addr.0.i395, align 1
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%conv612.i397 = sext i8 %9 to i32
128+
%sub13.i398 = add nsw i32 %conv612.i397, -48
129+
%cmp714.i399 = icmp ugt i32 %sub13.i398, 9
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%10 = load i8, i8* undef, align 1
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%cmp9.not.i500 = icmp eq i8 0, %10
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br label %land.lhs.true402.critedge
133+
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land.lhs.true402.critedge: ; preds = %if.end5.i400
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br i1 %cmp9.not.i500, label %if.then404, label %if.else407
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if.then404: ; preds = %land.lhs.true402.critedge
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br label %for.body564
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if.else407: ; preds = %land.lhs.true402.critedge
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br label %if.end570
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for.body564: ; preds = %for.body564, %if.then404
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%i560.0801 = phi i32 [ 0, %if.then404 ], [ %inc568.31, %for.body564 ]
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%inc568.31 = add nuw nsw i32 %i560.0801, 32
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%exitcond839.not.31 = icmp eq i32 %inc568.31, 4096
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br i1 %exitcond839.not.31, label %if.end570, label %for.body564
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if.end570: ; preds = %for.body564, %if.else407
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unreachable
151+
152+
cleanup.cont: ; preds = %if.end15, %if.end
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ret void
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}
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attributes #0 = { "uniform-work-group-size"="true" }

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