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[RISCV] Remove experimental for Ssqosid ext (#105476)
Ratified: https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0
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‎clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -126,6 +126,7 @@
126126
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
127127
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
128128
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
129+
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
129130
// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
130131
// CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present)
131132
// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts)
@@ -178,7 +179,6 @@
178179
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
179180
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
180181
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
181-
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
182182
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
183183
// CHECK-EMPTY:
184184
// CHECK-NEXT: Supported Profiles

‎clang/test/Preprocessor/riscv-target-features.c

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
// CHECK-NOT: __riscv_sscofpmf {{.*$}}
3838
// CHECK-NOT: __riscv_sscounterenw {{.*$}}
3939
// CHECK-NOT: __riscv_sscsrind {{.*$}}
40+
// CHECK-NOT: __riscv_ssqosid{{.*$}}
4041
// CHECK-NOT: __riscv_ssstateen {{.*$}}
4142
// CHECK-NOT: __riscv_ssstrict {{.*$}}
4243
// CHECK-NOT: __riscv_sstc {{.*$}}
@@ -179,7 +180,6 @@
179180
// CHECK-NOT: __riscv_smnpm{{.*$}}
180181
// CHECK-NOT: __riscv_ssnpm{{.*$}}
181182
// CHECK-NOT: __riscv_sspm{{.*$}}
182-
// CHECK-NOT: __riscv_ssqosid{{.*$}}
183183
// CHECK-NOT: __riscv_supm{{.*$}}
184184
// CHECK-NOT: __riscv_zacas {{.*$}}
185185
// CHECK-NOT: __riscv_zalasr {{.*$}}
@@ -1415,6 +1415,14 @@
14151415
// RUN: -o - | FileCheck --check-prefix=CHECK-SSCSRIND-EXT %s
14161416
// CHECK-SSCSRIND-EXT: __riscv_sscsrind 1000000{{$}}
14171417

1418+
// RUN: %clang --target=riscv32 \
1419+
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
1420+
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
1421+
// RUN: %clang --target=riscv64 \
1422+
// RUN: -march=rv64i_ssqosid1p0 -E -dM %s \
1423+
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
1424+
// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}
1425+
14181426
// RUN: %clang --target=riscv32 \
14191427
// RUN: -march=rv32ismcdeleg1p0 -E -dM %s \
14201428
// RUN: -o - | FileCheck --check-prefix=CHECK-SMCDELEG-EXT %s
@@ -1740,14 +1748,6 @@
17401748
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
17411749
// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}
17421750

1743-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1744-
// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \
1745-
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
1746-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1747-
// RUN: -march=rv64i_ssqosid1p0 -E -dM %s \
1748-
// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s
1749-
// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}}
1750-
17511751
// Misaligned
17521752

17531753
// RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \

‎llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,7 @@ on support follow.
136136
``Sscofpmf`` Assembly Support
137137
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
138138
``Sscsrind`` Supported
139+
``Ssqosid`` Assembly Support
139140
``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
140141
``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
141142
``Sstc`` Assembly Support
@@ -290,9 +291,6 @@ The primary goal of experimental support is to assist in the process of ratifica
290291
``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
291292
LLVM implements the `v1.0.0-rc2 specification <https://github.com/riscv/riscv-j-extension/releases/tag/pointer-masking-v1.0.0-rc2>`__.
292293

293-
``experimental-ssqosid``
294-
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.
295-
296294
``experimental-zacas``
297295
LLVM implements the `1.0 release specification <https://github.com/riscvarchive/riscv-zacas/releases/tag/v1.0>`__. amocas.w will be used for i32 cmpxchg. amocas.d will be used i64 cmpxchg on RV64. The compiler will not generate amocas.d on RV32 or amocas.q on RV64 due to ABI compatibilty. These can only be used in the assembler. The extension will be left as experimental until `an ABI issue <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/444>`__ is resolved.
298296

‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -968,9 +968,9 @@ def FeatureStdExtSstc
968968
: RISCVExtension<"sstc", 1, 0,
969969
"'Sstc' (Supervisor-mode timer interrupts)">;
970970

971-
def FeaturesStdExtSsqosid
972-
: RISCVExperimentalExtension<"ssqosid", 1, 0,
973-
"'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;
971+
def FeatureStdExtSsqosid
972+
: RISCVExtension<"ssqosid", 1, 0,
973+
"'Ssqosid' (Quality-of-Service (QoS) Identifiers)">;
974974

975975
def FeatureStdExtShtvala
976976
: RISCVExtension<"shtvala", 1, 0,

‎llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,7 @@
115115
; RUN: llc -mtriple=riscv32 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
116116
; RUN: llc -mtriple=riscv32 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCSRIND %s
117117
; RUN: llc -mtriple=riscv32 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV32SSCSRIND %s
118+
; RUN: llc -mtriple=riscv32 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
118119
; RUN: llc -mtriple=riscv32 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV32SMCDELEG %s
119120
; RUN: llc -mtriple=riscv32 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV32SMEPMP %s
120121
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
@@ -132,7 +133,6 @@
132133
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
133134
; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
134135
; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
135-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s
136136

137137
; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
138138
; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -256,6 +256,7 @@
256256
; RUN: llc -mtriple=riscv64 -mattr=+ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
257257
; RUN: llc -mtriple=riscv64 -mattr=+smcsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCSRIND %s
258258
; RUN: llc -mtriple=riscv64 -mattr=+sscsrind %s -o - | FileCheck --check-prefixes=CHECK,RV64SSCSRIND %s
259+
; RUN: llc -mtriple=riscv64 -mattr=+ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
259260
; RUN: llc -mtriple=riscv64 -mattr=+smcdeleg %s -o - | FileCheck --check-prefixes=CHECK,RV64SMCDELEG %s
260261
; RUN: llc -mtriple=riscv64 -mattr=+smepmp %s -o - | FileCheck --check-prefixes=CHECK,RV64SMEPMP %s
261262
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
@@ -272,7 +273,6 @@
272273
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
273274
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
274275
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
275-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s
276276

277277
; Tests for profile features.
278278
; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s
@@ -403,6 +403,7 @@
403403
; RV32SSAIA: .attribute 5, "rv32i2p1_ssaia1p0"
404404
; RV32SMCSRIND: .attribute 5, "rv32i2p1_smcsrind1p0"
405405
; RV32SSCSRIND: .attribute 5, "rv32i2p1_sscsrind1p0"
406+
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
406407
; RV32SMCDELEG: .attribute 5, "rv32i2p1_smcdeleg1p0"
407408
; RV32SMEPMP: .attribute 5, "rv32i2p1_smepmp1p0"
408409
; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -420,7 +421,6 @@
420421
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm1p0"
421422
; RV32SSPM: .attribute 5, "rv32i2p1_sspm1p0"
422423
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
423-
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"
424424

425425
; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
426426
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
@@ -542,6 +542,7 @@
542542
; RV64SSAIA: .attribute 5, "rv64i2p1_ssaia1p0"
543543
; RV64SMCSRIND: .attribute 5, "rv64i2p1_smcsrind1p0"
544544
; RV64SSCSRIND: .attribute 5, "rv64i2p1_sscsrind1p0"
545+
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
545546
; RV64SMCDELEG: .attribute 5, "rv64i2p1_smcdeleg1p0"
546547
; RV64SMEPMP: .attribute 5, "rv64i2p1_smepmp1p0"
547548
; RV64ZFBFMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0"
@@ -558,7 +559,6 @@
558559
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm1p0"
559560
; RV64SSPM: .attribute 5, "rv64i2p1_sspm1p0"
560561
; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
561-
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"
562562

563563
; RVI20U32: .attribute 5, "rv32i2p1"
564564
; RVI20U64: .attribute 5, "rv64i2p1"

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1071,6 +1071,7 @@ R"(All available -march extensions for RISC-V
10711071
sscofpmf 1.0
10721072
sscounterenw 1.0
10731073
sscsrind 1.0
1074+
ssqosid 1.0
10741075
ssstateen 1.0
10751076
ssstrict 1.0
10761077
sstc 1.0
@@ -1123,7 +1124,6 @@ Experimental extensions
11231124
smnpm 1.0
11241125
ssnpm 1.0
11251126
sspm 1.0
1126-
ssqosid 1.0
11271127
supm 1.0
11281128
11291129
Supported Profiles

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