Skip to content

Commit bb17651

Browse files
s-barannikovs-barannikov
authored
[TTI] Simplify implementation (NFCI) (#136674)
Replace "concept based polymorphism" with simpler PImpl idiom. This pursues two goals: * Enforce static type checking. Previously, target implementations hid base class methods and type checking was impossible. Now that they override the methods, the compiler will complain on mismatched signatures. * Make the code easier to navigate. Previously, if you asked your favorite LSP server to show a method (e.g. `getInstructionCost()`), it would show you methods from `TTI`, `TTI::Concept`, `TTI::Model`, `TTIImplBase`, and target overrides. Now it is two less :) There are three commits to hopefully simplify the review. The first commit removes `TTI::Model`. This is done by deriving `TargetTransformInfoImplBase` from `TTI::Concept`. This is possible because they implement the same set of interfaces with identical signatures. The first commit makes `TargetTransformImplBase` polymorphic, which means all derived classes should `override` its methods. This is done in second commit to make the first one smaller. It appeared infeasible to extract this into a separate PR because the first commit landed separately would result in tons of `-Woverloaded-virtual` warnings (and break `-Werror` builds). The third commit eliminates `TTI::Concept` by merging it with the only derived class `TargetTransformImplBase`. This commit could be extracted into a separate PR, but it touches the same lines in `TargetTransformInfoImpl.h` (removes `override` added by the second commit and adds `virtual`), so I thought it may make sense to land these two commits together. Pull Request: #136674
1 parent 28293ea commit bb17651

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

46 files changed

+1337
-2545
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h

Lines changed: 4 additions & 1356 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Lines changed: 399 additions & 329 deletions
Large diffs are not rendered by default.

‎llvm/include/llvm/CodeGen/BasicTTIImpl.h

Lines changed: 153 additions & 140 deletions
Large diffs are not rendered by default.

‎llvm/lib/Analysis/TargetTransformInfo.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,10 @@ struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
5757
};
5858
} // namespace
5959

60+
TargetTransformInfo::TargetTransformInfo(
61+
std::unique_ptr<const TargetTransformInfoImplBase> Impl)
62+
: TTIImpl(std::move(Impl)) {}
63+
6064
bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
6165
// If the loop has irreducible control flow, it can not be converted to
6266
// Hardware loop.
@@ -199,7 +203,7 @@ bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
199203
}
200204

201205
TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
202-
: TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
206+
: TTIImpl(std::make_unique<NoTTIImpl>(DL)) {}
203207

204208
TargetTransformInfo::~TargetTransformInfo() = default;
205209

@@ -1472,7 +1476,7 @@ void TargetTransformInfo::collectKernelLaunchBounds(
14721476
return TTIImpl->collectKernelLaunchBounds(F, LB);
14731477
}
14741478

1475-
TargetTransformInfo::Concept::~Concept() = default;
1479+
TargetTransformInfoImplBase::~TargetTransformInfoImplBase() = default;
14761480

14771481
TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
14781482

‎llvm/lib/CodeGen/CodeGenTargetMachineImpl.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ CodeGenTargetMachineImpl::CodeGenTargetMachineImpl(
103103

104104
TargetTransformInfo
105105
CodeGenTargetMachineImpl::getTargetTransformInfo(const Function &F) const {
106-
return TargetTransformInfo(BasicTTIImpl(this, F));
106+
return TargetTransformInfo(std::make_unique<BasicTTIImpl>(this, F));
107107
}
108108

109109
/// addPassesToX helper drives creation and initialization of TargetPassConfig.

‎llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -582,7 +582,7 @@ void AArch64TargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
582582

583583
TargetTransformInfo
584584
AArch64TargetMachine::getTargetTransformInfo(const Function &F) const {
585-
return TargetTransformInfo(AArch64TTIImpl(this, F));
585+
return TargetTransformInfo(std::make_unique<AArch64TTIImpl>(this, F));
586586
}
587587

588588
TargetPassConfig *AArch64TargetMachine::createPassConfig(PassManagerBase &PM) {

‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h

Lines changed: 124 additions & 112 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1070,7 +1070,7 @@ GCNTargetMachine::getSubtargetImpl(const Function &F) const {
10701070

10711071
TargetTransformInfo
10721072
GCNTargetMachine::getTargetTransformInfo(const Function &F) const {
1073-
return TargetTransformInfo(GCNTTIImpl(this, F));
1073+
return TargetTransformInfo(std::make_unique<GCNTTIImpl>(this, F));
10741074
}
10751075

10761076
Error GCNTargetMachine::buildCodeGenPipeline(

‎llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h

Lines changed: 65 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
//===----------------------------------------------------------------------===//
88
//
99
/// \file
10-
/// This file a TargetTransformInfo::Concept conforming object specific to the
10+
/// This file a TargetTransformInfoImplBase conforming object specific to the
1111
/// AMDGPU target machine. It uses the target's detailed information to
1212
/// provide more precise answers to certain TTI queries, while letting the
1313
/// target independent and default TTI implementations handle the rest.
@@ -52,12 +52,12 @@ class AMDGPUTTIImpl final : public BasicTTIImplBase<AMDGPUTTIImpl> {
5252

5353
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
5454
TTI::UnrollingPreferences &UP,
55-
OptimizationRemarkEmitter *ORE) const;
55+
OptimizationRemarkEmitter *ORE) const override;
5656

5757
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
58-
TTI::PeelingPreferences &PP) const;
58+
TTI::PeelingPreferences &PP) const override;
5959

60-
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
60+
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
6161
};
6262

6363
class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
@@ -104,64 +104,65 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
104104
public:
105105
explicit GCNTTIImpl(const AMDGPUTargetMachine *TM, const Function &F);
106106

107-
bool hasBranchDivergence(const Function *F = nullptr) const;
107+
bool hasBranchDivergence(const Function *F = nullptr) const override;
108108

109109
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
110110
TTI::UnrollingPreferences &UP,
111-
OptimizationRemarkEmitter *ORE) const;
111+
OptimizationRemarkEmitter *ORE) const override;
112112

113113
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
114-
TTI::PeelingPreferences &PP) const;
114+
TTI::PeelingPreferences &PP) const override;
115115

116-
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const {
116+
TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override {
117117
assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
118118
return TTI::PSK_FastHardware;
119119
}
120120

121-
unsigned getNumberOfRegisters(unsigned RCID) const;
122-
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
123-
unsigned getMinVectorRegisterBitWidth() const;
124-
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
121+
unsigned getNumberOfRegisters(unsigned RCID) const override;
122+
TypeSize
123+
getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
124+
unsigned getMinVectorRegisterBitWidth() const override;
125+
unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const override;
125126
unsigned getLoadVectorFactor(unsigned VF, unsigned LoadSize,
126127
unsigned ChainSizeInBytes,
127-
VectorType *VecTy) const;
128+
VectorType *VecTy) const override;
128129
unsigned getStoreVectorFactor(unsigned VF, unsigned StoreSize,
129130
unsigned ChainSizeInBytes,
130-
VectorType *VecTy) const;
131-
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
131+
VectorType *VecTy) const override;
132+
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
132133

133134
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
134135
unsigned AddrSpace) const;
135136
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
136-
unsigned AddrSpace) const;
137+
unsigned AddrSpace) const override;
137138
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
138-
unsigned AddrSpace) const;
139+
unsigned AddrSpace) const override;
139140

140-
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const;
141-
Type *
142-
getMemcpyLoopLoweringType(LLVMContext &Context, Value *Length,
143-
unsigned SrcAddrSpace, unsigned DestAddrSpace,
144-
Align SrcAlign, Align DestAlign,
145-
std::optional<uint32_t> AtomicElementSize) const;
141+
uint64_t getMaxMemIntrinsicInlineSizeThreshold() const override;
142+
Type *getMemcpyLoopLoweringType(
143+
LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
144+
unsigned DestAddrSpace, Align SrcAlign, Align DestAlign,
145+
std::optional<uint32_t> AtomicElementSize) const override;
146146

147147
void getMemcpyLoopResidualLoweringType(
148148
SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
149149
unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
150150
Align SrcAlign, Align DestAlign,
151-
std::optional<uint32_t> AtomicCpySize) const;
152-
unsigned getMaxInterleaveFactor(ElementCount VF) const;
151+
std::optional<uint32_t> AtomicCpySize) const override;
152+
unsigned getMaxInterleaveFactor(ElementCount VF) const override;
153153

154-
bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info) const;
154+
bool getTgtMemIntrinsic(IntrinsicInst *Inst,
155+
MemIntrinsicInfo &Info) const override;
155156

156157
InstructionCost getArithmeticInstrCost(
157158
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
158159
TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
159160
TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
160161
ArrayRef<const Value *> Args = {},
161-
const Instruction *CxtI = nullptr) const;
162+
const Instruction *CxtI = nullptr) const override;
162163

163164
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
164-
const Instruction *I = nullptr) const;
165+
const Instruction *I = nullptr) const override;
165166

166167
bool isInlineAsmSourceOfDivergence(const CallInst *CI,
167168
ArrayRef<unsigned> Indices = {}) const;
@@ -170,13 +171,13 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
170171
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
171172
TTI::TargetCostKind CostKind,
172173
unsigned Index, Value *Op0,
173-
Value *Op1) const;
174+
Value *Op1) const override;
174175

175176
bool isReadRegisterSourceOfDivergence(const IntrinsicInst *ReadReg) const;
176-
bool isSourceOfDivergence(const Value *V) const;
177-
bool isAlwaysUniform(const Value *V) const;
177+
bool isSourceOfDivergence(const Value *V) const override;
178+
bool isAlwaysUniform(const Value *V) const override;
178179

179-
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const {
180+
bool isValidAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
180181
// Address space casts must cast between different address spaces.
181182
if (FromAS == ToAS)
182183
return false;
@@ -197,11 +198,11 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
197198
return false;
198199
}
199200

200-
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const {
201+
bool addrspacesMayAlias(unsigned AS0, unsigned AS1) const override {
201202
return AMDGPU::addrspacesMayAlias(AS0, AS1);
202203
}
203204

204-
unsigned getFlatAddressSpace() const {
205+
unsigned getFlatAddressSpace() const override {
205206
// Don't bother running InferAddressSpaces pass on graphics shaders which
206207
// don't use flat addressing.
207208
if (IsGraphics)
@@ -210,24 +211,25 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
210211
}
211212

212213
bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
213-
Intrinsic::ID IID) const;
214+
Intrinsic::ID IID) const override;
214215

215-
bool canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const {
216+
bool
217+
canHaveNonUndefGlobalInitializerInAddressSpace(unsigned AS) const override {
216218
return AS != AMDGPUAS::LOCAL_ADDRESS && AS != AMDGPUAS::REGION_ADDRESS &&
217219
AS != AMDGPUAS::PRIVATE_ADDRESS;
218220
}
219221

220222
Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
221-
Value *NewV) const;
223+
Value *NewV) const override;
222224

223225
bool canSimplifyLegacyMulToMul(const Instruction &I, const Value *Op0,
224226
const Value *Op1, InstCombiner &IC) const;
225227

226228
bool simplifyDemandedLaneMaskArg(InstCombiner &IC, IntrinsicInst &II,
227229
unsigned LaneAgIdx) const;
228230

229-
std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
230-
IntrinsicInst &II) const;
231+
std::optional<Instruction *>
232+
instCombineIntrinsic(InstCombiner &IC, IntrinsicInst &II) const override;
231233

232234
Value *simplifyAMDGCNLaneIntrinsicDemanded(InstCombiner &IC,
233235
IntrinsicInst &II,
@@ -238,40 +240,43 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
238240
InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
239241
APInt &UndefElts2, APInt &UndefElts3,
240242
std::function<void(Instruction *, unsigned, APInt, APInt &)>
241-
SimplifyAndSetOp) const;
243+
SimplifyAndSetOp) const override;
242244

243245
InstructionCost getVectorSplitCost() const { return 0; }
244246

245-
InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
246-
ArrayRef<int> Mask,
247-
TTI::TargetCostKind CostKind, int Index,
248-
VectorType *SubTp,
249-
ArrayRef<const Value *> Args = {},
250-
const Instruction *CxtI = nullptr) const;
247+
InstructionCost
248+
getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef<int> Mask,
249+
TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,
250+
ArrayRef<const Value *> Args = {},
251+
const Instruction *CxtI = nullptr) const override;
251252

252253
bool isProfitableToSinkOperands(Instruction *I,
253-
SmallVectorImpl<Use *> &Ops) const;
254+
SmallVectorImpl<Use *> &Ops) const override;
254255

255256
bool areInlineCompatible(const Function *Caller,
256-
const Function *Callee) const;
257+
const Function *Callee) const override;
257258

258-
int getInliningLastCallToStaticBonus() const;
259-
unsigned getInliningThresholdMultiplier() const { return 11; }
260-
unsigned adjustInliningThreshold(const CallBase *CB) const;
261-
unsigned getCallerAllocaCost(const CallBase *CB, const AllocaInst *AI) const;
259+
int getInliningLastCallToStaticBonus() const override;
260+
unsigned getInliningThresholdMultiplier() const override { return 11; }
261+
unsigned adjustInliningThreshold(const CallBase *CB) const override;
262+
unsigned getCallerAllocaCost(const CallBase *CB,
263+
const AllocaInst *AI) const override;
262264

263-
int getInlinerVectorBonusPercent() const { return InlinerVectorBonusPercent; }
265+
int getInlinerVectorBonusPercent() const override {
266+
return InlinerVectorBonusPercent;
267+
}
264268

265269
InstructionCost
266270
getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
267271
std::optional<FastMathFlags> FMF,
268-
TTI::TargetCostKind CostKind) const;
272+
TTI::TargetCostKind CostKind) const override;
269273

270-
InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
271-
TTI::TargetCostKind CostKind) const;
272-
InstructionCost getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty,
273-
FastMathFlags FMF,
274-
TTI::TargetCostKind CostKind) const;
274+
InstructionCost
275+
getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
276+
TTI::TargetCostKind CostKind) const override;
277+
InstructionCost
278+
getMinMaxReductionCost(Intrinsic::ID IID, VectorType *Ty, FastMathFlags FMF,
279+
TTI::TargetCostKind CostKind) const override;
275280

276281
/// Data cache line size for LoopDataPrefetch pass. Has no use before GFX12.
277282
unsigned getCacheLineSize() const override { return 128; }
@@ -284,7 +289,7 @@ class GCNTTIImpl final : public BasicTTIImplBase<GCNTTIImpl> {
284289
bool shouldPrefetchAddressSpace(unsigned AS) const override;
285290
void collectKernelLaunchBounds(
286291
const Function &F,
287-
SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const;
292+
SmallVectorImpl<std::pair<StringRef, int64_t>> &LB) const override;
288293
};
289294

290295
} // end namespace llvm

‎llvm/lib/Target/AMDGPU/R600TargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ R600TargetMachine::getSubtargetImpl(const Function &F) const {
8787

8888
TargetTransformInfo
8989
R600TargetMachine::getTargetTransformInfo(const Function &F) const {
90-
return TargetTransformInfo(R600TTIImpl(this, F));
90+
return TargetTransformInfo(std::make_unique<R600TTIImpl>(this, F));
9191
}
9292

9393
ScheduleDAGInstrs *

‎llvm/lib/Target/AMDGPU/R600TargetTransformInfo.h

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
//===----------------------------------------------------------------------===//
88
//
99
/// \file
10-
/// This file a TargetTransformInfo::Concept conforming object specific to the
10+
/// This file a TargetTransformInfoImplBase conforming object specific to the
1111
/// R600 target machine. It uses the target's detailed information to
1212
/// provide more precise answers to certain TTI queries, while letting the
1313
/// target independent and default TTI implementations handle the rest.
@@ -43,28 +43,29 @@ class R600TTIImpl final : public BasicTTIImplBase<R600TTIImpl> {
4343

4444
void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
4545
TTI::UnrollingPreferences &UP,
46-
OptimizationRemarkEmitter *ORE) const;
46+
OptimizationRemarkEmitter *ORE) const override;
4747
void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
48-
TTI::PeelingPreferences &PP) const;
48+
TTI::PeelingPreferences &PP) const override;
4949
unsigned getHardwareNumberOfRegisters(bool Vec) const;
50-
unsigned getNumberOfRegisters(unsigned ClassID) const;
51-
TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const;
52-
unsigned getMinVectorRegisterBitWidth() const;
53-
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const;
50+
unsigned getNumberOfRegisters(unsigned ClassID) const override;
51+
TypeSize
52+
getRegisterBitWidth(TargetTransformInfo::RegisterKind Vector) const override;
53+
unsigned getMinVectorRegisterBitWidth() const override;
54+
unsigned getLoadStoreVecRegBitWidth(unsigned AddrSpace) const override;
5455
bool isLegalToVectorizeMemChain(unsigned ChainSizeInBytes, Align Alignment,
5556
unsigned AddrSpace) const;
5657
bool isLegalToVectorizeLoadChain(unsigned ChainSizeInBytes, Align Alignment,
57-
unsigned AddrSpace) const;
58+
unsigned AddrSpace) const override;
5859
bool isLegalToVectorizeStoreChain(unsigned ChainSizeInBytes, Align Alignment,
59-
unsigned AddrSpace) const;
60-
unsigned getMaxInterleaveFactor(ElementCount VF) const;
60+
unsigned AddrSpace) const override;
61+
unsigned getMaxInterleaveFactor(ElementCount VF) const override;
6162
InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
62-
const Instruction *I = nullptr) const;
63+
const Instruction *I = nullptr) const override;
6364
using BaseT::getVectorInstrCost;
6465
InstructionCost getVectorInstrCost(unsigned Opcode, Type *ValTy,
6566
TTI::TargetCostKind CostKind,
6667
unsigned Index, Value *Op0,
67-
Value *Op1) const;
68+
Value *Op1) const override;
6869
};
6970

7071
} // end namespace llvm

‎llvm/lib/Target/ARC/ARCTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -103,5 +103,5 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARCTarget() {
103103

104104
TargetTransformInfo
105105
ARCTargetMachine::getTargetTransformInfo(const Function &F) const {
106-
return TargetTransformInfo(ARCTTIImpl(this, F));
106+
return TargetTransformInfo(std::make_unique<ARCTTIImpl>(this, F));
107107
}

‎llvm/lib/Target/ARC/ARCTargetTransformInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
//
77
//===----------------------------------------------------------------------===//
88
// \file
9-
// This file contains a TargetTransformInfo::Concept conforming object specific
9+
// This file contains a TargetTransformInfoImplBase conforming object specific
1010
// to the ARC target machine. It uses the target's detailed information to
1111
// provide more precise answers to certain TTI queries, while letting the
1212
// target independent and default TTI implementations handle the rest.

‎llvm/lib/Target/ARM/ARMTargetMachine.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -322,7 +322,7 @@ ARMBaseTargetMachine::getSubtargetImpl(const Function &F) const {
322322

323323
TargetTransformInfo
324324
ARMBaseTargetMachine::getTargetTransformInfo(const Function &F) const {
325-
return TargetTransformInfo(ARMTTIImpl(this, F));
325+
return TargetTransformInfo(std::make_unique<ARMTTIImpl>(this, F));
326326
}
327327

328328
ScheduleDAGInstrs *

0 commit comments

Comments
 (0)