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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3 |
| 2 | +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 -O0 -verify-machineinstrs --stop-after=regallocfast,1 -o - %s | FileCheck -check-prefix=REGALLOC %s |
| 3 | + |
| 4 | +; FIXME: There are two spill codes inserted wrongly in this test. |
| 5 | +; They are inserted during regalloc for the BBLiveIns - the spill restores for vgpr1 in the Flow block (bb.1) and for vgpr0 in the return block (bb.4). |
| 6 | +define i32 @prolog_spill(i32 %arg0, i32 %arg1, i32 %arg2) { |
| 7 | + ; REGALLOC-LABEL: name: prolog_spill |
| 8 | + ; REGALLOC: bb.0.bb.0: |
| 9 | + ; REGALLOC-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000) |
| 10 | + ; REGALLOC-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2 |
| 11 | + ; REGALLOC-NEXT: {{ $}} |
| 12 | + ; REGALLOC-NEXT: renamable $vgpr3 = IMPLICIT_DEF |
| 13 | + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr2, %stack.5, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.5, addrspace 5) |
| 14 | + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.4, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.4, addrspace 5) |
| 15 | + ; REGALLOC-NEXT: renamable $vgpr1 = COPY killed $vgpr0 |
| 16 | + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) |
| 17 | + ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 49 |
| 18 | + ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = V_CMP_GT_I32_e64 killed $vgpr1, killed $sgpr4, implicit $exec |
| 19 | + ; REGALLOC-NEXT: renamable $sgpr6 = IMPLICIT_DEF |
| 20 | + ; REGALLOC-NEXT: renamable $vgpr1 = COPY killed renamable $sgpr6 |
| 21 | + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) |
| 22 | + ; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = COPY $exec, implicit-def $exec |
| 23 | + ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 renamable $sgpr6_sgpr7, killed renamable $sgpr4_sgpr5, implicit-def dead $scc |
| 24 | + ; REGALLOC-NEXT: renamable $sgpr6_sgpr7 = S_XOR_B64 renamable $sgpr4_sgpr5, killed renamable $sgpr6_sgpr7, implicit-def dead $scc |
| 25 | + ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 killed $sgpr6, 0, $vgpr0, implicit-def $sgpr6_sgpr7, implicit $sgpr6_sgpr7 |
| 26 | + ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 killed $sgpr7, 1, $vgpr0, implicit killed $sgpr6_sgpr7 |
| 27 | + ; REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr0, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) |
| 28 | + ; REGALLOC-NEXT: $exec = S_MOV_B64_term killed renamable $sgpr4_sgpr5 |
| 29 | + ; REGALLOC-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec |
| 30 | + ; REGALLOC-NEXT: S_BRANCH %bb.3 |
| 31 | + ; REGALLOC-NEXT: {{ $}} |
| 32 | + ; REGALLOC-NEXT: bb.1.Flow: |
| 33 | + ; REGALLOC-NEXT: successors: %bb.2(0x40000000), %bb.4(0x40000000) |
| 34 | + ; REGALLOC-NEXT: {{ $}} |
| 35 | + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) |
| 36 | + ; REGALLOC-NEXT: $vgpr1 = SI_SPILL_V32_RESTORE %stack.3, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.3, addrspace 5) |
| 37 | + ; REGALLOC-NEXT: $sgpr4 = V_READLANE_B32 $vgpr0, 0, implicit-def $sgpr4_sgpr5 |
| 38 | + ; REGALLOC-NEXT: $sgpr5 = V_READLANE_B32 $vgpr0, 1 |
| 39 | + ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_OR_SAVEEXEC_B64 killed renamable $sgpr4_sgpr5, implicit-def $exec, implicit-def dead $scc, implicit $exec |
| 40 | + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr1, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) |
| 41 | + ; REGALLOC-NEXT: renamable $sgpr4_sgpr5 = S_AND_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc |
| 42 | + ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 killed $sgpr4, 2, $vgpr0, implicit-def $sgpr4_sgpr5, implicit $sgpr4_sgpr5 |
| 43 | + ; REGALLOC-NEXT: renamable $vgpr0 = V_WRITELANE_B32 $sgpr5, 3, $vgpr0, implicit $sgpr4_sgpr5 |
| 44 | + ; REGALLOC-NEXT: SI_SPILL_WWM_V32_SAVE killed $vgpr0, %stack.2, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.2, addrspace 5) |
| 45 | + ; REGALLOC-NEXT: $exec = S_XOR_B64_term $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc |
| 46 | + ; REGALLOC-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec |
| 47 | + ; REGALLOC-NEXT: S_BRANCH %bb.2 |
| 48 | + ; REGALLOC-NEXT: {{ $}} |
| 49 | + ; REGALLOC-NEXT: bb.2.bb.1: |
| 50 | + ; REGALLOC-NEXT: successors: %bb.4(0x80000000) |
| 51 | + ; REGALLOC-NEXT: {{ $}} |
| 52 | + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.4, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.4, addrspace 5) |
| 53 | + ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 10 |
| 54 | + ; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec |
| 55 | + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.6, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.6, addrspace 5) |
| 56 | + ; REGALLOC-NEXT: S_BRANCH %bb.4 |
| 57 | + ; REGALLOC-NEXT: {{ $}} |
| 58 | + ; REGALLOC-NEXT: bb.3.bb.2: |
| 59 | + ; REGALLOC-NEXT: successors: %bb.1(0x80000000) |
| 60 | + ; REGALLOC-NEXT: {{ $}} |
| 61 | + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.5, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.5, addrspace 5) |
| 62 | + ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 20 |
| 63 | + ; REGALLOC-NEXT: renamable $vgpr0 = V_ADD_U32_e64 $vgpr0, killed $sgpr4, 0, implicit $exec |
| 64 | + ; REGALLOC-NEXT: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr32, 0, implicit $exec :: (store (s32) into %stack.3, addrspace 5) |
| 65 | + ; REGALLOC-NEXT: S_BRANCH %bb.1 |
| 66 | + ; REGALLOC-NEXT: {{ $}} |
| 67 | + ; REGALLOC-NEXT: bb.4.bb.3: |
| 68 | + ; REGALLOC-NEXT: $vgpr1 = SI_SPILL_WWM_V32_RESTORE %stack.2, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.2, addrspace 5) |
| 69 | + ; REGALLOC-NEXT: $vgpr0 = SI_SPILL_V32_RESTORE %stack.6, $sgpr32, 0, implicit $exec :: (load (s32) from %stack.6, addrspace 5) |
| 70 | + ; REGALLOC-NEXT: $sgpr4 = V_READLANE_B32 $vgpr1, 2, implicit-def $sgpr4_sgpr5 |
| 71 | + ; REGALLOC-NEXT: $sgpr5 = V_READLANE_B32 $vgpr1, 3 |
| 72 | + ; REGALLOC-NEXT: $exec = S_OR_B64 $exec, killed renamable $sgpr4_sgpr5, implicit-def dead $scc |
| 73 | + ; REGALLOC-NEXT: renamable $sgpr4 = S_MOV_B32 5 |
| 74 | + ; REGALLOC-NEXT: renamable $vgpr0 = V_MUL_LO_U32_e64 killed $vgpr0, killed $sgpr4, implicit $exec |
| 75 | + ; REGALLOC-NEXT: KILL killed renamable $vgpr1 |
| 76 | + ; REGALLOC-NEXT: SI_RETURN implicit killed $vgpr0 |
| 77 | +bb.0: |
| 78 | + %cmp = icmp slt i32 %arg0, 50 |
| 79 | + br i1 %cmp, label %bb.1, label %bb.2 |
| 80 | + |
| 81 | +bb.1: |
| 82 | + %val1 = add i32 %arg1, 10 |
| 83 | + br label %bb.3 |
| 84 | + |
| 85 | +bb.2: |
| 86 | + %val2 = add i32 %arg2, 20 |
| 87 | + br label %bb.3 |
| 88 | + |
| 89 | +bb.3: |
| 90 | + %val = phi i32 [ %val1, %bb.1 ], [ %val2, %bb.2 ] |
| 91 | + %ret = mul i32 %val, 5; |
| 92 | + ret i32 %ret |
| 93 | +} |
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