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[AArch64][SVE] Add missing unwind info for SVE registers.
This patch adds a CFI entry for each SVE callee saved register that needs unwind info at an offset from the CFA. The offset is a DWARF expression because the offset is partly scalable. The CFI entries only cover a subset of the SVE callee-saves and only encodes the lower 64-bits, thus implementing the lowest common denominator ABI. Existing unwinders may support VG but only restore the lower 64-bits. Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D84044
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6 files changed

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-34
lines changed

6 files changed

+142
-34
lines changed

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 54 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -458,12 +458,44 @@ MCCFIInstruction AArch64FrameLowering::createDefCFAExpressionFromSP(
458458
Comment.str());
459459
}
460460

461+
MCCFIInstruction AArch64FrameLowering::createCfaOffset(
462+
const TargetRegisterInfo &TRI, unsigned Reg,
463+
const StackOffset &OffsetFromDefCFA) const {
464+
int64_t NumBytes, NumVGScaledBytes;
465+
OffsetFromDefCFA.getForDwarfOffset(NumBytes, NumVGScaledBytes);
466+
467+
unsigned DwarfReg = TRI.getDwarfRegNum(Reg, true);
468+
469+
// Non-scalable offsets can use DW_CFA_offset directly.
470+
if (!NumVGScaledBytes)
471+
return MCCFIInstruction::createOffset(nullptr, DwarfReg, NumBytes);
472+
473+
std::string CommentBuffer;
474+
llvm::raw_string_ostream Comment(CommentBuffer);
475+
Comment << printReg(Reg, &TRI) << " @ cfa";
476+
477+
// Build up expression (NumBytes + NumVGScaledBytes * AArch64::VG)
478+
SmallString<64> OffsetExpr;
479+
appendVGScaledOffsetExpr(OffsetExpr, NumBytes, NumVGScaledBytes,
480+
TRI.getDwarfRegNum(AArch64::VG, true), Comment);
481+
482+
// Wrap this into DW_CFA_expression
483+
SmallString<64> CfaExpr;
484+
CfaExpr.push_back(dwarf::DW_CFA_expression);
485+
uint8_t buffer[16];
486+
CfaExpr.append(buffer, buffer + encodeULEB128(DwarfReg, buffer));
487+
CfaExpr.append(buffer, buffer + encodeULEB128(OffsetExpr.size(), buffer));
488+
CfaExpr.append(OffsetExpr.str());
489+
490+
return MCCFIInstruction::createEscape(nullptr, CfaExpr.str(), Comment.str());
491+
}
492+
461493
void AArch64FrameLowering::emitCalleeSavedFrameMoves(
462494
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI) const {
463495
MachineFunction &MF = *MBB.getParent();
464496
MachineFrameInfo &MFI = MF.getFrameInfo();
465497
const TargetSubtargetInfo &STI = MF.getSubtarget();
466-
const MCRegisterInfo *MRI = STI.getRegisterInfo();
498+
const TargetRegisterInfo *TRI = STI.getRegisterInfo();
467499
const TargetInstrInfo *TII = STI.getInstrInfo();
468500
DebugLoc DL = MBB.findDebugLoc(MBBI);
469501

@@ -474,11 +506,26 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves(
474506

475507
for (const auto &Info : CSI) {
476508
unsigned Reg = Info.getReg();
477-
int64_t Offset =
478-
MFI.getObjectOffset(Info.getFrameIdx()) - getOffsetOfLocalArea();
479-
unsigned DwarfReg = MRI->getDwarfRegNum(Reg, true);
480-
unsigned CFIIndex = MF.addFrameInst(
481-
MCCFIInstruction::createOffset(nullptr, DwarfReg, Offset));
509+
510+
// Not all unwinders may know about SVE registers, so assume the lowest
511+
// common demoninator.
512+
unsigned NewReg;
513+
if (static_cast<const AArch64RegisterInfo *>(TRI)->regNeedsCFI(Reg, NewReg))
514+
Reg = NewReg;
515+
else
516+
continue;
517+
518+
StackOffset Offset;
519+
if (MFI.getStackID(Info.getFrameIdx()) == TargetStackID::SVEVector) {
520+
AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
521+
Offset = StackOffset(MFI.getObjectOffset(Info.getFrameIdx()), MVT::nxv1i8) -
522+
StackOffset(AFI->getCalleeSavedStackSize(MFI), MVT::i8);
523+
} else {
524+
Offset = {MFI.getObjectOffset(Info.getFrameIdx()) -
525+
getOffsetOfLocalArea(),
526+
MVT::i8};
527+
}
528+
unsigned CFIIndex = MF.addFrameInst(createCfaOffset(*TRI, Reg, Offset));
482529
BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
483530
.addCFIIndex(CFIIndex)
484531
.setMIFlags(MachineInstr::FrameSetup);
@@ -2074,6 +2121,7 @@ static void computeCalleeSaveRegisterPairs(
20742121
// available unwind codes. This flag assures that the alignment fixup is done
20752122
// only once, as intened.
20762123
bool FixupDone = false;
2124+
20772125
for (unsigned i = 0; i < Count; ++i) {
20782126
RegPairInfo RPI;
20792127
RPI.Reg1 = CSI[i].getReg();

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -124,7 +124,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
124124
MCCFIInstruction
125125
createDefCFAExpressionFromSP(const TargetRegisterInfo &TRI,
126126
const StackOffset &OffsetFromSP) const;
127-
MCCFIInstruction createCfaOffset(const MCRegisterInfo &MRI, unsigned DwarfReg,
127+
MCCFIInstruction createCfaOffset(const TargetRegisterInfo &MRI, unsigned DwarfReg,
128128
const StackOffset &OffsetFromDefCFA) const;
129129
bool shouldCombineCSRLocalStackBumpInEpilogue(MachineBasicBlock &MBB,
130130
unsigned StackBumpBytes) const;

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,29 @@ AArch64RegisterInfo::AArch64RegisterInfo(const Triple &TT)
4040
AArch64_MC::initLLVMToCVRegMapping(this);
4141
}
4242

43+
/// Return whether the register needs a CFI entry. Not all unwinders may know
44+
/// about SVE registers, so we assume the lowest common denominator, i.e. the
45+
/// callee-saves required by the base ABI. For the SVE registers z8-z15 only the
46+
/// lower 64-bits (d8-d15) need to be saved. The lower 64-bits subreg is
47+
/// returned in \p RegToUseForCFI.
48+
bool AArch64RegisterInfo::regNeedsCFI(unsigned Reg,
49+
unsigned &RegToUseForCFI) const {
50+
if (AArch64::PPRRegClass.contains(Reg))
51+
return false;
52+
53+
if (AArch64::ZPRRegClass.contains(Reg)) {
54+
RegToUseForCFI = getSubReg(Reg, AArch64::dsub);
55+
for (int I = 0; CSR_AArch64_AAPCS_SaveList[I]; ++I) {
56+
if (CSR_AArch64_AAPCS_SaveList[I] == RegToUseForCFI)
57+
return true;
58+
}
59+
return false;
60+
}
61+
62+
RegToUseForCFI = Reg;
63+
return true;
64+
}
65+
4366
static bool hasSVEArgsOrReturn(const MachineFunction *MF) {
4467
const Function &F = MF->getFunction();
4568
return isa<ScalableVectorType>(F.getReturnType()) ||

‎llvm/lib/Target/AArch64/AArch64RegisterInfo.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -122,6 +122,7 @@ class AArch64RegisterInfo final : public AArch64GenRegisterInfo {
122122
MachineFunction &MF) const override;
123123

124124
unsigned getLocalAddressRegister(const MachineFunction &MF) const;
125+
bool regNeedsCFI(unsigned Reg, unsigned &RegToUseForCFI) const;
125126
};
126127

127128
} // end namespace llvm

‎llvm/test/CodeGen/AArch64/framelayout-sve.mir

Lines changed: 63 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -449,7 +449,7 @@ body: |
449449
# CHECK: frame-setup STR_PXI killed $p5, $sp, 6
450450
# CHECK: frame-setup STR_PXI killed $p4, $sp, 7
451451
# CHECK: $sp = frame-setup SUBXri $sp, 32, 0
452-
# CHECK-COUNT-5: frame-setup CFI_INSTRUCTION
452+
# CHECK-COUNT-2: frame-setup CFI_INSTRUCTION
453453

454454
# CHECK: $sp = frame-destroy ADDXri $sp, 32, 0
455455
# CHECK: $p6 = frame-destroy LDR_PXI $sp, 5
@@ -460,11 +460,9 @@ body: |
460460
#
461461
# ASM-LABEL: save_restore_pregs_sve:
462462
# ASM: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x30, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 48 + 8 * VG
463-
# ASM-COUNT-3: .cfi_offset
464463
# ASM-NEXT: .cfi_offset w29, -16
465464
#
466465
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +48, DW_OP_plus, DW_OP_consts +8, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
467-
# UNWINDINFO-COUNT-3: DW_CFA_offset
468466
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
469467
name: save_restore_pregs_sve
470468
stack:
@@ -498,11 +496,16 @@ body: |
498496
#
499497
# ASM-LABEL: save_restore_zregs_sve:
500498
# ASM: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x30, 0x22, 0x11, 0x18, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 48 + 24 * VG
501-
# ASM-COUNT-3: .cfi_offset
502-
#
503-
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +48, DW_OP_plus, DW_OP_consts +24, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
504-
# UNWINDINFO-COUNT-3: DW_CFA_offset
505-
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
499+
# ASM-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
500+
# ASM-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
501+
# ASM-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG
502+
503+
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +48, DW_OP_plus, DW_OP_consts +24, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
504+
# UNWINDINFO-NEXT: DW_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
505+
# UNWINDINFO-NEXT: DW_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
506+
# UNWINDINFO-NEXT: DW_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
507+
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
508+
506509
name: save_restore_zregs_sve
507510
stack:
508511
- { id: 0, stack-id: default, size: 32, alignment: 16 }
@@ -536,7 +539,7 @@ body: |
536539
# CHECK: frame-setup STR_ZXI killed $z8, $sp, 17
537540
# CHECK: $sp = frame-setup ADDVL_XXI $sp, -1
538541
# CHECK: $sp = frame-setup SUBXri $sp, 32, 0
539-
# CHECK-COUNT-33: frame-setup CFI_INSTRUCTION
542+
# CHECK-COUNT-13: frame-setup CFI_INSTRUCTION
540543

541544
# CHECK: $sp = frame-destroy ADDXri $sp, 32, 0
542545
# CHECK: $sp = frame-destroy ADDVL_XXI $sp, 1
@@ -555,18 +558,32 @@ body: |
555558
#
556559
# ASM-LABEL: save_restore_sve:
557560
# ASM: .cfi_escape 0x0f, 0x0e, 0x8f, 0x00, 0x11, 0xc0, 0x00, 0x22, 0x11, 0x98, 0x01, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 64 + 152 * VG
558-
# ASM-COUNT-28: .cfi_offset
561+
# ASM-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 32 - 8 * VG
562+
# ASM-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 32 - 16 * VG
563+
# ASM-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 32 - 24 * VG
564+
# ASM-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 32 - 32 * VG
565+
# ASM-NEXT: .cfi_escape 0x10, 0x4c, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x58, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d12 @ cfa - 32 - 40 * VG
566+
# ASM-NEXT: .cfi_escape 0x10, 0x4d, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x50, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d13 @ cfa - 32 - 48 * VG
567+
# ASM-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x48, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 32 - 56 * VG
568+
# ASM-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x60, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 32 - 64 * VG
559569
# ASM-NEXT: .cfi_offset w19, -8
560570
# ASM-NEXT: .cfi_offset w20, -16
561571
# ASM-NEXT: .cfi_offset w21, -24
562572
# ASM-NEXT: .cfi_offset w29, -32
563573
#
564-
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +64, DW_OP_plus, DW_OP_consts +152, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
565-
# UNWINDINFO-COUNT-28: DW_CFA_offset
566-
# UNWINDINFO-NEXT: DW_CFA_offset: reg19 -8
567-
# UNWINDINFO-NEXT: DW_CFA_offset: reg20 -16
568-
# UNWINDINFO-NEXT: DW_CFA_offset: reg21 -24
569-
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -32
574+
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +64, DW_OP_plus, DW_OP_consts +152, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
575+
# UNWINDINFO-NEXT: DW_CFA_expression: reg72 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
576+
# UNWINDINFO-NEXT: DW_CFA_expression: reg73 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
577+
# UNWINDINFO-NEXT: DW_CFA_expression: reg74 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
578+
# UNWINDINFO-NEXT: DW_CFA_expression: reg75 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
579+
# UNWINDINFO-NEXT: DW_CFA_expression: reg76 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
580+
# UNWINDINFO-NEXT: DW_CFA_expression: reg77 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
581+
# UNWINDINFO-NEXT: DW_CFA_expression: reg78 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -56, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
582+
# UNWINDINFO-NEXT: DW_CFA_expression: reg79 DW_OP_consts -32, DW_OP_plus, DW_OP_consts -64, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
583+
# UNWINDINFO-NEXT: DW_CFA_offset: reg19 -8
584+
# UNWINDINFO-NEXT: DW_CFA_offset: reg20 -16
585+
# UNWINDINFO-NEXT: DW_CFA_offset: reg21 -24
586+
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -32
570587

571588
name: save_restore_sve
572589
stack:
@@ -620,7 +637,7 @@ body: |
620637
# CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -1
621638
# CHECK-NEXT: $[[TMP:x[0-9]+]] = frame-setup SUBXri $sp, 16, 0
622639
# CHECK-NEXT: $sp = ANDXri killed $[[TMP]]
623-
# CHECK-COUNT-31: frame-setup CFI_INSTRUCTION
640+
# CHECK-COUNT-11: frame-setup CFI_INSTRUCTION
624641

625642
# CHECK: $sp = frame-destroy ADDVL_XXI $fp, -18
626643
# CHECK-NEXT: $p15 = frame-destroy LDR_PXI $sp, 4
@@ -635,10 +652,30 @@ body: |
635652
# CHECK-NEXT: $sp, $fp, $lr = frame-destroy LDPXpost $sp, 2
636653
# CHECK-NEXT: RET_ReallyLR
637654
#
638-
# UNWINDINFO: DW_CFA_def_cfa: reg29 +16
639-
# UNWINDINFO-COUNT-28: DW_CFA_offset
640-
# UNWINDINFO-NEXT: DW_CFA_offset: reg30 -8
641-
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
655+
# ASM-LABEL: save_restore_sve_realign:
656+
# ASM: .cfi_def_cfa w29, 16
657+
# ASM-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
658+
# ASM-NEXT: .cfi_escape 0x10, 0x49, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x70, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d9 @ cfa - 16 - 16 * VG
659+
# ASM-NEXT: .cfi_escape 0x10, 0x4a, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x68, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d10 @ cfa - 16 - 24 * VG
660+
# ASM-NEXT: .cfi_escape 0x10, 0x4b, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x60, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d11 @ cfa - 16 - 32 * VG
661+
# ASM-NEXT: .cfi_escape 0x10, 0x4c, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x58, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d12 @ cfa - 16 - 40 * VG
662+
# ASM-NEXT: .cfi_escape 0x10, 0x4d, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x50, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d13 @ cfa - 16 - 48 * VG
663+
# ASM-NEXT: .cfi_escape 0x10, 0x4e, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x48, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d14 @ cfa - 16 - 56 * VG
664+
# ASM-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 16 - 64 * VG
665+
# ASM-NEXT: .cfi_offset w30, -8
666+
# ASM-NEXT: .cfi_offset w29, -16
667+
#
668+
# UNWINDINFO: DW_CFA_def_cfa: reg29 +16
669+
# UNWINDINFO-NEXT: DW_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
670+
# UNWINDINFO-NEXT: DW_CFA_expression: reg73 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -16, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
671+
# UNWINDINFO-NEXT: DW_CFA_expression: reg74 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -24, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
672+
# UNWINDINFO-NEXT: DW_CFA_expression: reg75 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -32, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
673+
# UNWINDINFO-NEXT: DW_CFA_expression: reg76 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -40, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
674+
# UNWINDINFO-NEXT: DW_CFA_expression: reg77 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -48, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
675+
# UNWINDINFO-NEXT: DW_CFA_expression: reg78 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -56, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
676+
# UNWINDINFO-NEXT: DW_CFA_expression: reg79 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -64, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
677+
# UNWINDINFO-NEXT: DW_CFA_offset: reg30 -8
678+
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
642679
name: save_restore_sve_realign
643680
stack:
644681
- { id: 0, stack-id: sve-vec, size: 16, alignment: 16 }
@@ -713,15 +750,15 @@ body: |
713750
# CHECK-NEXT: STR_ZXI killed $z23, $sp, 1
714751
# CHECK-NEXT: STR_ZXI killed $z8, $sp, 2
715752
# CHECK-NEXT: $sp = frame-setup ADDVL_XXI $sp, -7
716-
# CHECK-COUNT-6: frame-setup CFI_INSTRUCTION
753+
# CHECK-COUNT-3: frame-setup CFI_INSTRUCTION
717754
# ASM-LABEL: frame_layout:
718755
# ASM: .cfi_escape 0x0f, 0x0d, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd0, 0x00, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 80 * VG
719-
# ASM-COUNT-4: .cfi_offset
756+
# ASM-NEXT: .cfi_escape 0x10, 0x48, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x78, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d8 @ cfa - 16 - 8 * VG
720757
# ASM-NEXT: .cfi_offset w29, -16
721758
#
722-
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +16, DW_OP_plus, DW_OP_consts +80, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
723-
# UNWINDINFO-COUNT-4: DW_CFA_offset
724-
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
759+
# UNWINDINFO: DW_CFA_def_cfa_expression: DW_OP_breg31 +0, DW_OP_consts +16, DW_OP_plus, DW_OP_consts +80, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
760+
# UNWINDINFO-NEXT: DW_CFA_expression: reg72 DW_OP_consts -16, DW_OP_plus, DW_OP_consts -8, DW_OP_bregx 0x2e +0, DW_OP_mul, DW_OP_plus
761+
# UNWINDINFO-NEXT: DW_CFA_offset: reg29 -16
725762
name: frame_layout
726763
stack:
727764
- { id: 0, type: default, size: 32, alignment: 16, stack-id: sve-vec }

‎llvm/test/CodeGen/AArch64/sve-trunc.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,6 @@ define <vscale x 16 x i1> @trunc_i64toi1_split3(<vscale x 16 x i64> %in) {
117117
; CHECK-NEXT: addvl sp, sp, #-1
118118
; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Folded Spill
119119
; CHECK-NEXT: .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
120-
; CHECK-NEXT: .cfi_offset p4, -2
121120
; CHECK-NEXT: .cfi_offset w29, -16
122121
; CHECK-NEXT: ptrue p0.d
123122
; CHECK-NEXT: and z7.d, z7.d, #0x1

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