Skip to content

Commit bb37f12

Browse files
fhahnfhahn
committed
[SCEV] Check AR's wrap flags when expanding in non-post increment loops.
dcc84db introduced the IsIncrementNUW/NSW helpers instead of checking the AddRecs wrap flags, with the reason being that the increment by one in the post-inc form may wrap, even if the original AddRec would not wrap. AFAICT there is only an issue with loops in post-inc form. This patch brings back checking the original check of the no-wrap flags on AR, if AR's loop isn't in the set of post-inc loops.
1 parent 59d6f03 commit bb37f12

15 files changed

+34
-24
lines changed

‎llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -854,7 +854,12 @@ static bool IsIncrementNSW(ScalarEvolution &SE, const SCEVAddRecExpr *AR) {
854854
SE.getSignExtendExpr(AR, WideTy));
855855
const SCEV *ExtendAfterOp =
856856
SE.getSignExtendExpr(SE.getAddExpr(AR, Step), WideTy);
857-
return ExtendAfterOp == OpAfterExtend;
857+
if (ExtendAfterOp == OpAfterExtend)
858+
return true;
859+
860+
// Check AR's flags last. Constructing the SCEVs above may strengthen NoWrap
861+
// flags for constructed AddRecs
862+
return AR->getNoWrapFlags(SCEV::FlagNSW);
858863
}
859864

860865
static bool IsIncrementNUW(ScalarEvolution &SE, const SCEVAddRecExpr *AR) {
@@ -868,7 +873,12 @@ static bool IsIncrementNUW(ScalarEvolution &SE, const SCEVAddRecExpr *AR) {
868873
SE.getZeroExtendExpr(AR, WideTy));
869874
const SCEV *ExtendAfterOp =
870875
SE.getZeroExtendExpr(SE.getAddExpr(AR, Step), WideTy);
871-
return ExtendAfterOp == OpAfterExtend;
876+
if (ExtendAfterOp == OpAfterExtend)
877+
return true;
878+
879+
// Check AR's flags last. Constructing the SCEVs above may strengthen NoWrap
880+
// flags for constructed AddRecs
881+
return AR->getNoWrapFlags(SCEV::FlagNUW);
872882
}
873883

874884
/// getAddRecExprPHILiterally - Helper for expandAddRecExprLiterally. Expand

‎llvm/test/Transforms/IndVarSimplify/lftr-reuse.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,7 @@ define void @expandOuterRecurrence(i32 %arg) nounwind {
8686
; CHECK-NEXT: br label [[OUTER_INC]]
8787
; CHECK: outer.inc:
8888
; CHECK-NEXT: [[I_INC]] = add nuw nsw i32 [[I]], 1
89-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], -1
89+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i32 [[INDVARS_IV]], -1
9090
; CHECK-NEXT: [[EXITCOND1:%.*]] = icmp ne i32 [[I_INC]], [[SUB1]]
9191
; CHECK-NEXT: br i1 [[EXITCOND1]], label [[OUTER]], label [[EXIT_LOOPEXIT:%.*]]
9292
; CHECK: exit.loopexit:
@@ -148,7 +148,7 @@ define void @guardedloop(ptr %matrix, ptr %vector,
148148
; CHECK-NEXT: [[VECTORP:%.*]] = getelementptr inbounds [0 x double], ptr [[VECTOR:%.*]], i32 0, i64 [[INDVARS_IV2]]
149149
; CHECK-NEXT: [[V2:%.*]] = load double, ptr [[VECTORP]], align 8
150150
; CHECK-NEXT: call void @use(double [[V2]])
151-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], [[TMP0]]
151+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], [[TMP0]]
152152
; CHECK-NEXT: [[INDVARS_IV_NEXT3]] = add nuw nsw i64 [[INDVARS_IV2]], 1
153153
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT3]], [[WIDE_TRIP_COUNT]]
154154
; CHECK-NEXT: br i1 [[EXITCOND]], label [[LOOP]], label [[RETURN_LOOPEXIT:%.*]]

‎llvm/test/Transforms/IndVarSimplify/pr30806-phi-scev.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,7 @@ define void @foo(ptr %buf, i32 %denominator, ptr %flag) local_unnamed_addr {
4343
; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[WHILE_BODY]] ], [ 0, [[WHILE_BODY_LR_PH]] ]
4444
; CHECK-NEXT: [[BUF_ADDR_07:%.*]] = phi ptr [ [[BUF]], [[WHILE_BODY_LR_PH]] ], [ [[CALL:%.*]], [[WHILE_BODY]] ]
4545
; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[DIV]] to i64
46-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], [[TMP2]]
46+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], [[TMP2]]
4747
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @theSize, align 4
4848
; CHECK-NEXT: store i32 [[TMP3]], ptr [[I]], align 4
4949
; CHECK-NEXT: call void @bar(ptr nonnull [[I]], i64 [[INDVARS_IV_NEXT]])

‎llvm/test/Transforms/IndVarSimplify/pr55925.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define void @test(ptr %p) personality ptr undef {
1818
; CHECK-NEXT: [[RES:%.*]] = invoke i32 @foo(i32 returned [[TMP0]])
1919
; CHECK-NEXT: to label [[LOOP_LATCH]] unwind label [[EXIT:%.*]]
2020
; CHECK: loop.latch:
21-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
21+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw i64 [[INDVARS_IV]], 1
2222
; CHECK-NEXT: [[TMP1:%.*]] = trunc i64 [[INDVARS_IV]] to i32
2323
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @foo(i32 [[TMP1]])
2424
; CHECK-NEXT: br label [[LOOP]]
@@ -64,7 +64,7 @@ define void @test_critedge(i1 %c, ptr %p) personality ptr undef {
6464
; CHECK-NEXT: br label [[LOOP_LATCH]]
6565
; CHECK: loop.latch:
6666
; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[TMP1]], [[LOOP_INVOKE]] ], [ 0, [[LOOP_OTHER]] ]
67-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
67+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw i64 [[INDVARS_IV]], 1
6868
; CHECK-NEXT: [[TMP2:%.*]] = call i32 @foo(i32 [[PHI]])
6969
; CHECK-NEXT: br label [[LOOP]]
7070
; CHECK: exit:

‎llvm/test/Transforms/IndVarSimplify/preserve-nsw-during-expansion.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ define void @test_s172(i32 noundef %xa, i32 noundef %xb, ptr nocapture noundef %
2323
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4
2424
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], [[TMP2]]
2525
; CHECK-NEXT: store i32 [[ADD]], ptr [[ARRAYIDX2]], align 4
26-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], [[TMP1]]
26+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], [[TMP1]]
2727
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[INDVARS_IV_NEXT]], 32000
2828
; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_END_LOOPEXIT:%.*]], !llvm.loop [[LOOP0:![0-9]+]]
2929
; CHECK: for.end.loopexit:

‎llvm/test/Transforms/IndVarSimplify/widen-i32-i8ptr.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ define dso_local void @Widen_i32_i8ptr() local_unnamed_addr {
1515
; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i8, ptr [[GID_0]], i64 1
1616
; CHECK-NEXT: [[ARRAYIDX2115:%.*]] = getelementptr inbounds [15 x ptr], ptr [[PTRIDS]], i64 0, i64 [[INDVARS_IV]]
1717
; CHECK-NEXT: store ptr [[GID_0]], ptr [[ARRAYIDX2115]], align 8
18-
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw i64 [[INDVARS_IV]], 1
18+
; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
1919
; CHECK-NEXT: br label [[FOR_COND2106]]
2020
;
2121
entry:

‎llvm/test/Transforms/LoopStrengthReduce/AArch64/postinc-with-fixups-with-different-loops.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ define i32 @test() {
2222
; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[LSR_IV_NEXT2_LCSSA]], [[LOOP_2_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_2]] ]
2323
; CHECK-NEXT: call void @use(i32 [[IV_2]])
2424
; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1
25-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], -1
25+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], -1
2626
; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
2727
; CHECK-NEXT: br i1 [[EC]], label [[EXIT:%.*]], label [[LOOP_2]]
2828
; CHECK: exit:

‎llvm/test/Transforms/LoopStrengthReduce/ARM/illegal-addr-modes.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ target triple = "thumbv6m-arm-none-eabi"
1818

1919
; Test case 01: -1*reg is not free for the Thumb1 target.
2020
define ptr @negativeOneCase(ptr returned %a, ptr nocapture readonly %b, i32 %n) nounwind {
21-
; CHECK-LABEL: define ptr @negativeOneCase
22-
; CHECK-SAME: (ptr returned [[A:%.*]], ptr nocapture readonly [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
21+
; CHECK-LABEL: define ptr @negativeOneCase(
22+
; CHECK-SAME: ptr returned [[A:%.*]], ptr nocapture readonly [[B:%.*]], i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2323
; CHECK-NEXT: entry:
2424
; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[A]], i32 -1
2525
; CHECK-NEXT: br label [[WHILE_COND:%.*]]
@@ -40,7 +40,7 @@ define ptr @negativeOneCase(ptr returned %a, ptr nocapture readonly %b, i32 %n)
4040
; CHECK: while.body5:
4141
; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr [[SCEVGEP1]], align 1
4242
; CHECK-NEXT: store i8 [[TMP1]], ptr [[SCEVGEP2]], align 1
43-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
43+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw i32 [[LSR_IV]], 1
4444
; CHECK-NEXT: br label [[WHILE_COND2]]
4545
; CHECK: while.end8:
4646
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[INCDEC_PTR]], i32 [[N]]
@@ -85,8 +85,8 @@ while.end8: ; preds = %while.cond2
8585
; Test case 02: 4*reg({0,+,-1}) and -4*reg({0,+,-1}) are not supported for
8686
; the Thumb1 target.
8787
define void @negativeFourCase(ptr %ptr1, ptr %ptr2) nounwind {
88-
; CHECK-LABEL: define void @negativeFourCase
89-
; CHECK-SAME: (ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) #[[ATTR0]] {
88+
; CHECK-LABEL: define void @negativeFourCase(
89+
; CHECK-SAME: ptr [[PTR1:%.*]], ptr [[PTR2:%.*]]) #[[ATTR0]] {
9090
; CHECK-NEXT: entry:
9191
; CHECK-NEXT: br label [[FOR_COND6_PREHEADER_US_I_I:%.*]]
9292
; CHECK: for.cond6.preheader.us.i.i:

‎llvm/test/Transforms/LoopStrengthReduce/RISCV/icmp-zero.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -358,7 +358,7 @@ define void @loop_invariant_definition(i64 %arg) {
358358
; CHECK-NEXT: br label [[T1:%.*]]
359359
; CHECK: t1:
360360
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[T1]] ], [ -1, [[ENTRY:%.*]] ]
361-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 1
361+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1
362362
; CHECK-NEXT: br i1 true, label [[T4:%.*]], label [[T1]]
363363
; CHECK: t4:
364364
; CHECK-NEXT: [[T5:%.*]] = trunc i64 [[LSR_IV_NEXT]] to i32

‎llvm/test/Transforms/LoopStrengthReduce/X86/expander-crashes.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ define i64 @blam(ptr %start, ptr %end, ptr %ptr.2) {
3535
; CHECK-NEXT: br i1 [[EC_2]], label [[LOOP_2_EXIT:%.*]], label [[LOOP_2_LATCH]]
3636
; CHECK: loop.2.latch:
3737
; CHECK-NEXT: [[IV2_NEXT]] = getelementptr inbounds [[STRUCT_HOGE]], ptr [[IV2]], i64 1
38-
; CHECK-NEXT: [[LSR_IV_NEXT3]] = add i64 [[LSR_IV2]], 16
38+
; CHECK-NEXT: [[LSR_IV_NEXT3]] = add nuw i64 [[LSR_IV2]], 16
3939
; CHECK-NEXT: br label [[LOOP_2_HEADER]]
4040
; CHECK: loop.2.exit:
4141
; CHECK-NEXT: ret i64 [[LSR_IV2]]

‎llvm/test/Transforms/LoopStrengthReduce/X86/postinc-iv-used-by-urem-and-udiv.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ define i64 @test_pr58039() {
5454
; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[IV]] to i32
5555
; CHECK-NEXT: call void @use.i32(i32 [[TMP2]])
5656
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
57-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 4294967295
57+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 4294967295
5858
; CHECK-NEXT: br i1 false, label [[LOOP]], label [[EXIT:%.*]]
5959
; CHECK: exit:
6060
; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 [[LSR_IV_NEXT]], 12

‎llvm/test/Transforms/LoopStrengthReduce/X86/pr40514.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ define i32 @pluto(i32 %arg) #0 {
1414
; CHECK: bb10:
1515
; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2]], [[BB10]] ], [ 9, [[BB:%.*]] ]
1616
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT]], [[BB10]] ], [ undef, [[BB]] ]
17-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], 1
17+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i32 [[LSR_IV]], 1
1818
; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nuw nsw i64 [[LSR_IV1]], 1
1919
; CHECK-NEXT: br i1 true, label [[BB1:%.*]], label [[BB10]]
2020
;

‎llvm/test/Transforms/LoopStrengthReduce/X86/pr62660-normalization-failure.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ define i64 @test_pr62660() {
1717
; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[IV]], -1
1818
; CHECK-NEXT: [[SUB:%.*]] = add i32 [[ADD]], [[CONV1]]
1919
; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
20-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 1
20+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1
2121
; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[SUB]], 8
2222
; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT:%.*]]
2323
; CHECK: exit:
@@ -82,8 +82,8 @@ define void @pr63840_crash(i64 %sext974, i64 %sext982, i8 %x) {
8282
; CHECK-NEXT: [[LSR_IV3:%.*]] = phi i64 [ [[LSR_IV_NEXT4]], [[BB1059]] ], [ [[LSR_IV1]], [[BB992]] ]
8383
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB1059]] ], [ -1, [[BB992]] ]
8484
; CHECK-NEXT: [[PHI1094]] = phi i64 [ [[LSR_IV_NEXT8_LCSSA]], [[BB992]] ], [ [[ADD1054]], [[BB1059]] ]
85-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 1
86-
; CHECK-NEXT: [[LSR_IV_NEXT4]] = add i64 [[LSR_IV3]], [[SEXT1046]]
85+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1
86+
; CHECK-NEXT: [[LSR_IV_NEXT4]] = add nuw nsw i64 [[LSR_IV3]], [[SEXT1046]]
8787
; CHECK-NEXT: [[ICMP1050:%.*]] = icmp ult i64 [[LSR_IV_NEXT]], 0
8888
; CHECK-NEXT: br i1 [[ICMP1050]], label [[BB1053:%.*]], label [[BB1051:%.*]]
8989
;

‎llvm/test/Transforms/LoopStrengthReduce/nonintegral.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ define void @japi1__unsafe_getindex_65028(ptr addrspace(10) %arg) {
1616
; CHECK-NEXT: br label [[L86:%.*]]
1717
; CHECK: L86:
1818
; CHECK-NEXT: [[LSR_IV4:%.*]] = phi i64 [ [[LSR_IV_NEXT5:%.*]], [[L86]] ], [ -2, [[TOP:%.*]] ]
19-
; CHECK-NEXT: [[LSR_IV_NEXT5]] = add nsw i64 [[LSR_IV4]], 2
19+
; CHECK-NEXT: [[LSR_IV_NEXT5]] = add nuw nsw i64 [[LSR_IV4]], 2
2020
; CHECK-NEXT: br i1 false, label [[L86]], label [[IF29:%.*]]
2121
; CHECK: if29:
2222
; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr addrspace(10) [[ARG]], i64 -8

‎llvm/test/Transforms/LoopStrengthReduce/wrong-hoisting-iv.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ define void @test1() {
2626
; CHECK: bb7:
2727
; CHECK-NEXT: [[LSR_IV1:%.*]] = phi i32 [ [[LSR_IV_NEXT2:%.*]], [[BB32:%.*]] ], [ 0, [[BB:%.*]] ]
2828
; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[BB32]] ], [ -8, [[BB]] ]
29-
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nsw i64 [[LSR_IV]], 8
29+
; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 8
3030
; CHECK-NEXT: [[LSR_IV_NEXT2]] = add nuw nsw i32 [[LSR_IV1]], [[TMP5]]
3131
; CHECK-NEXT: [[VAL10:%.*]] = icmp ult i64 [[LSR_IV_NEXT]], 65536
3232
; CHECK-NEXT: br i1 [[VAL10]], label [[BB12:%.*]], label [[BB11:%.*]]

0 commit comments

Comments
 (0)