[RISCV] Merge some test checks rvv/fixed-vectors-masked-gather.ll [nfc]

Author: preames

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

@@ -1,12 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=ilp32d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32V
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32V
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -target-abi=lp64d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64V
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64V
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+d,+zfh,+zvfh,+zve32f,+zvl128b -target-abi=ilp32d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV32,RV32ZVE32F
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,RV32ZVE32F
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+d,+zfh,+zvfh,+zve32f,+zvl128b -target-abi=lp64d \
-; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=RV64ZVE32F
+; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64ZVE32F
 
 declare <1 x i8> @llvm.masked.gather.v1i8.v1p0(<1 x ptr>, i32, <1 x i1>, <1 x i8>)
 
@@ -12915,23 +12915,11 @@ define <4 x i32> @mgather_broadcast_load_unmasked(ptr %base) {
 
 ; Same as previous, but use an explicit splat instead of splat-via-gep
 define <4 x i32> @mgather_broadcast_load_unmasked2(ptr %base) {
-; RV32-LABEL: mgather_broadcast_load_unmasked2:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; RV32-NEXT:    vlse32.v v8, (a0), zero
-; RV32-NEXT:    ret
-;
-; RV64V-LABEL: mgather_broadcast_load_unmasked2:
-; RV64V:       # %bb.0:
-; RV64V-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; RV64V-NEXT:    vlse32.v v8, (a0), zero
-; RV64V-NEXT:    ret
-;
-; RV64ZVE32F-LABEL: mgather_broadcast_load_unmasked2:
-; RV64ZVE32F:       # %bb.0:
-; RV64ZVE32F-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; RV64ZVE32F-NEXT:    vlse32.v v8, (a0), zero
-; RV64ZVE32F-NEXT:    ret
+; CHECK-LABEL: mgather_broadcast_load_unmasked2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT:    vlse32.v v8, (a0), zero
+; CHECK-NEXT:    ret
   %head = insertelement <4 x i1> poison, i1 true, i32 0
   %allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
   %ptrhead = insertelement <4 x ptr> poison, ptr %base, i32 0
@@ -13598,21 +13586,13 @@ define <8 x i16> @mgather_shuffle_reverse(ptr %base) {
 ; RV32-NEXT:    vrgather.vv v8, v9, v10
 ; RV32-NEXT:    ret
 ;
-; RV64V-LABEL: mgather_shuffle_reverse:
-; RV64V:       # %bb.0:
-; RV64V-NEXT:    addi a0, a0, 14
-; RV64V-NEXT:    li a1, -2
-; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64V-NEXT:    vlse16.v v8, (a0), a1
-; RV64V-NEXT:    ret
-;
-; RV64ZVE32F-LABEL: mgather_shuffle_reverse:
-; RV64ZVE32F:       # %bb.0:
-; RV64ZVE32F-NEXT:    addi a0, a0, 14
-; RV64ZVE32F-NEXT:    li a1, -2
-; RV64ZVE32F-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64ZVE32F-NEXT:    vlse16.v v8, (a0), a1
-; RV64ZVE32F-NEXT:    ret
+; RV64-LABEL: mgather_shuffle_reverse:
+; RV64:       # %bb.0:
+; RV64-NEXT:    addi a0, a0, 14
+; RV64-NEXT:    li a1, -2
+; RV64-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
+; RV64-NEXT:    vlse16.v v8, (a0), a1
+; RV64-NEXT:    ret
   %head = insertelement <8 x i1> poison, i1 true, i16 0
   %allones = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer
   %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64>  <i64 7, i64 6, i64 5, i64 4, i64 3, i64 2, i64 1, i64 0>