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[ARM] Classification Improvements to ARM Sched-Model. NFCI.
This is the second in the series of patches to enable adding of machine sched-models for ARM processors easier and compact. This patch focuses on integer instructions and adds missing sched definitions. Reviewers: rovka, rengolin Differential Revision: https://reviews.llvm.org/D29127 llvm-svn: 293935
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6 files changed

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‎llvm/lib/Target/ARM/ARMInstrInfo.td

Lines changed: 100 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -3899,7 +3899,8 @@ def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
38993899
(ins GPRnopc:$Rn, GPRnopc:$Rm),
39003900
IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
39013901
[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))]>,
3902-
Requires<[IsARM, HasV6]> {
3902+
Requires<[IsARM, HasV6]>,
3903+
Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
39033904
let Inst{15-12} = 0b0000;
39043905
let Unpredictable{15-12} = 0b1111;
39053906
}
@@ -3910,14 +3911,16 @@ def MULv5: ARMPseudoExpand<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm,
39103911
4, IIC_iMUL32,
39113912
[(set GPRnopc:$Rd, (mul GPRnopc:$Rn, GPRnopc:$Rm))],
39123913
(MUL GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, pred:$p, cc_out:$s)>,
3913-
Requires<[IsARM, NoV6, UseMulOps]>;
3914+
Requires<[IsARM, NoV6, UseMulOps]>,
3915+
Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
39143916
}
39153917

39163918
def MLA : AsMul1I32<0b0000001, (outs GPRnopc:$Rd),
39173919
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra),
39183920
IIC_iMAC32, "mla", "\t$Rd, $Rn, $Rm, $Ra",
39193921
[(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))]>,
3920-
Requires<[IsARM, HasV6, UseMulOps]> {
3922+
Requires<[IsARM, HasV6, UseMulOps]>,
3923+
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
39213924
bits<4> Ra;
39223925
let Inst{15-12} = Ra;
39233926
}
@@ -3928,12 +3931,14 @@ def MLAv5: ARMPseudoExpand<(outs GPRnopc:$Rd),
39283931
pred:$p, cc_out:$s), 4, IIC_iMAC32,
39293932
[(set GPRnopc:$Rd, (add (mul GPRnopc:$Rn, GPRnopc:$Rm), GPRnopc:$Ra))],
39303933
(MLA GPRnopc:$Rd, GPRnopc:$Rn, GPRnopc:$Rm, GPRnopc:$Ra, pred:$p, cc_out:$s)>,
3931-
Requires<[IsARM, NoV6]>;
3934+
Requires<[IsARM, NoV6]>,
3935+
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
39323936

39333937
def MLS : AMul1I<0b0000011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
39343938
IIC_iMAC32, "mls", "\t$Rd, $Rn, $Rm, $Ra",
39353939
[(set GPR:$Rd, (sub GPR:$Ra, (mul GPR:$Rn, GPR:$Rm)))]>,
3936-
Requires<[IsARM, HasV6T2, UseMulOps]> {
3940+
Requires<[IsARM, HasV6T2, UseMulOps]>,
3941+
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]> {
39373942
bits<4> Rd;
39383943
bits<4> Rm;
39393944
bits<4> Rn;
@@ -3950,43 +3955,50 @@ let isCommutable = 1 in {
39503955
def SMULL : AsMul1I64<0b0000110, (outs GPR:$RdLo, GPR:$RdHi),
39513956
(ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
39523957
"smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3953-
Requires<[IsARM, HasV6]>;
3958+
Requires<[IsARM, HasV6]>,
3959+
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
39543960

39553961
def UMULL : AsMul1I64<0b0000100, (outs GPR:$RdLo, GPR:$RdHi),
39563962
(ins GPR:$Rn, GPR:$Rm), IIC_iMUL64,
39573963
"umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3958-
Requires<[IsARM, HasV6]>;
3964+
Requires<[IsARM, HasV6]>,
3965+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL]>;
39593966

39603967
let Constraints = "@earlyclobber $RdLo,@earlyclobber $RdHi" in {
39613968
def SMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
39623969
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
39633970
4, IIC_iMUL64, [],
39643971
(SMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3965-
Requires<[IsARM, NoV6]>;
3972+
Requires<[IsARM, NoV6]>,
3973+
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
39663974

39673975
def UMULLv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
39683976
(ins GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s),
39693977
4, IIC_iMUL64, [],
39703978
(UMULL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s)>,
3971-
Requires<[IsARM, NoV6]>;
3979+
Requires<[IsARM, NoV6]>,
3980+
Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
39723981
}
39733982
}
39743983

39753984
// Multiply + accumulate
39763985
def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
39773986
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
39783987
"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3979-
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3988+
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
3989+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
39803990
def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
39813991
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi), IIC_iMAC64,
39823992
"umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3983-
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>;
3993+
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
3994+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
39843995

39853996
def UMAAL : AMul1I <0b0000010, (outs GPR:$RdLo, GPR:$RdHi),
39863997
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi),
39873998
IIC_iMAC64,
39883999
"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
3989-
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]> {
4000+
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">, Requires<[IsARM, HasV6]>,
4001+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]> {
39904002
bits<4> RdLo;
39914003
bits<4> RdHi;
39924004
bits<4> Rm;
@@ -4004,13 +4016,15 @@ def SMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
40044016
4, IIC_iMAC64, [],
40054017
(SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
40064018
pred:$p, cc_out:$s)>,
4007-
Requires<[IsARM, NoV6]>;
4019+
Requires<[IsARM, NoV6]>,
4020+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
40084021
def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
40094022
(ins GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi, pred:$p, cc_out:$s),
40104023
4, IIC_iMAC64, [],
40114024
(UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
40124025
pred:$p, cc_out:$s)>,
4013-
Requires<[IsARM, NoV6]>;
4026+
Requires<[IsARM, NoV6]>,
4027+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
40144028
}
40154029

40164030
} // hasSideEffects
@@ -4019,71 +4033,83 @@ def UMLALv5 : ARMPseudoExpand<(outs GPR:$RdLo, GPR:$RdHi),
40194033
def SMMUL : AMul2I <0b0111010, 0b0001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40204034
IIC_iMUL32, "smmul", "\t$Rd, $Rn, $Rm",
40214035
[(set GPR:$Rd, (mulhs GPR:$Rn, GPR:$Rm))]>,
4022-
Requires<[IsARM, HasV6]> {
4036+
Requires<[IsARM, HasV6]>,
4037+
Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
40234038
let Inst{15-12} = 0b1111;
40244039
}
40254040

40264041
def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40274042
IIC_iMUL32, "smmulr", "\t$Rd, $Rn, $Rm", []>,
4028-
Requires<[IsARM, HasV6]> {
4043+
Requires<[IsARM, HasV6]>,
4044+
Sched<[WriteMUL32, ReadMUL, ReadMUL]> {
40294045
let Inst{15-12} = 0b1111;
40304046
}
40314047

40324048
def SMMLA : AMul2Ia <0b0111010, 0b0001, (outs GPR:$Rd),
40334049
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
40344050
IIC_iMAC32, "smmla", "\t$Rd, $Rn, $Rm, $Ra",
40354051
[(set GPR:$Rd, (add (mulhs GPR:$Rn, GPR:$Rm), GPR:$Ra))]>,
4036-
Requires<[IsARM, HasV6, UseMulOps]>;
4052+
Requires<[IsARM, HasV6, UseMulOps]>,
4053+
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
40374054

40384055
def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
40394056
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
40404057
IIC_iMAC32, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
4041-
Requires<[IsARM, HasV6]>;
4058+
Requires<[IsARM, HasV6]>,
4059+
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
40424060

40434061
def SMMLS : AMul2Ia <0b0111010, 0b1101, (outs GPR:$Rd),
40444062
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
40454063
IIC_iMAC32, "smmls", "\t$Rd, $Rn, $Rm, $Ra", []>,
4046-
Requires<[IsARM, HasV6, UseMulOps]>;
4064+
Requires<[IsARM, HasV6, UseMulOps]>,
4065+
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
40474066

40484067
def SMMLSR : AMul2Ia <0b0111010, 0b1111, (outs GPR:$Rd),
40494068
(ins GPR:$Rn, GPR:$Rm, GPR:$Ra),
40504069
IIC_iMAC32, "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
4051-
Requires<[IsARM, HasV6]>;
4070+
Requires<[IsARM, HasV6]>,
4071+
Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
40524072

40534073
multiclass AI_smul<string opc> {
40544074
def BB : AMulxyI<0b0001011, 0b00, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40554075
IIC_iMUL16, !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
40564076
[(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16),
40574077
(sext_inreg GPR:$Rm, i16)))]>,
4058-
Requires<[IsARM, HasV5TE]>;
4078+
Requires<[IsARM, HasV5TE]>,
4079+
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
40594080

40604081
def BT : AMulxyI<0b0001011, 0b10, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40614082
IIC_iMUL16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
40624083
[(set GPR:$Rd, (mul (sext_inreg GPR:$Rn, i16),
40634084
(sra GPR:$Rm, (i32 16))))]>,
4064-
Requires<[IsARM, HasV5TE]>;
4085+
Requires<[IsARM, HasV5TE]>,
4086+
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
40654087

40664088
def TB : AMulxyI<0b0001011, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40674089
IIC_iMUL16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
40684090
[(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)),
40694091
(sext_inreg GPR:$Rm, i16)))]>,
4070-
Requires<[IsARM, HasV5TE]>;
4092+
Requires<[IsARM, HasV5TE]>,
4093+
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
40714094

40724095
def TT : AMulxyI<0b0001011, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40734096
IIC_iMUL16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
40744097
[(set GPR:$Rd, (mul (sra GPR:$Rn, (i32 16)),
40754098
(sra GPR:$Rm, (i32 16))))]>,
4076-
Requires<[IsARM, HasV5TE]>;
4099+
Requires<[IsARM, HasV5TE]>,
4100+
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
40774101

40784102
def WB : AMulxyI<0b0001001, 0b01, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40794103
IIC_iMUL16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
40804104
[]>,
4081-
Requires<[IsARM, HasV5TE]>;
4105+
Requires<[IsARM, HasV5TE]>,
4106+
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
40824107

40834108
def WT : AMulxyI<0b0001001, 0b11, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
40844109
IIC_iMUL16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
40854110
[]>,
4086-
Requires<[IsARM, HasV5TE]>;
4111+
Requires<[IsARM, HasV5TE]>,
4112+
Sched<[WriteMUL16, ReadMUL, ReadMUL]>;
40874113
}
40884114

40894115

@@ -4095,43 +4121,49 @@ multiclass AI_smla<string opc> {
40954121
[(set GPRnopc:$Rd, (add GPR:$Ra,
40964122
(mul (sext_inreg GPRnopc:$Rn, i16),
40974123
(sext_inreg GPRnopc:$Rm, i16))))]>,
4098-
Requires<[IsARM, HasV5TE, UseMulOps]>;
4124+
Requires<[IsARM, HasV5TE, UseMulOps]>,
4125+
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
40994126

41004127
def BT : AMulxyIa<0b0001000, 0b10, (outs GPRnopc:$Rd),
41014128
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
41024129
IIC_iMAC16, !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
41034130
[(set GPRnopc:$Rd,
41044131
(add GPR:$Ra, (mul (sext_inreg GPRnopc:$Rn, i16),
41054132
(sra GPRnopc:$Rm, (i32 16)))))]>,
4106-
Requires<[IsARM, HasV5TE, UseMulOps]>;
4133+
Requires<[IsARM, HasV5TE, UseMulOps]>,
4134+
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
41074135

41084136
def TB : AMulxyIa<0b0001000, 0b01, (outs GPRnopc:$Rd),
41094137
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
41104138
IIC_iMAC16, !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
41114139
[(set GPRnopc:$Rd,
41124140
(add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)),
41134141
(sext_inreg GPRnopc:$Rm, i16))))]>,
4114-
Requires<[IsARM, HasV5TE, UseMulOps]>;
4142+
Requires<[IsARM, HasV5TE, UseMulOps]>,
4143+
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
41154144

41164145
def TT : AMulxyIa<0b0001000, 0b11, (outs GPRnopc:$Rd),
41174146
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
41184147
IIC_iMAC16, !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
41194148
[(set GPRnopc:$Rd,
41204149
(add GPR:$Ra, (mul (sra GPRnopc:$Rn, (i32 16)),
41214150
(sra GPRnopc:$Rm, (i32 16)))))]>,
4122-
Requires<[IsARM, HasV5TE, UseMulOps]>;
4151+
Requires<[IsARM, HasV5TE, UseMulOps]>,
4152+
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
41234153

41244154
def WB : AMulxyIa<0b0001001, 0b00, (outs GPRnopc:$Rd),
41254155
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
41264156
IIC_iMAC16, !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
41274157
[]>,
4128-
Requires<[IsARM, HasV5TE, UseMulOps]>;
4158+
Requires<[IsARM, HasV5TE, UseMulOps]>,
4159+
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
41294160

41304161
def WT : AMulxyIa<0b0001001, 0b10, (outs GPRnopc:$Rd),
41314162
(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
41324163
IIC_iMAC16, !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
41334164
[]>,
4134-
Requires<[IsARM, HasV5TE, UseMulOps]>;
4165+
Requires<[IsARM, HasV5TE, UseMulOps]>,
4166+
Sched<[WriteMAC16, ReadMUL, ReadMUL, ReadMAC]>;
41354167
}
41364168
}
41374169

@@ -4142,22 +4174,26 @@ defm SMLA : AI_smla<"smla">;
41424174
def SMLALBB : AMulxyI64<0b0001010, 0b00, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
41434175
(ins GPRnopc:$Rn, GPRnopc:$Rm),
41444176
IIC_iMAC64, "smlalbb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4145-
Requires<[IsARM, HasV5TE]>;
4177+
Requires<[IsARM, HasV5TE]>,
4178+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
41464179

41474180
def SMLALBT : AMulxyI64<0b0001010, 0b10, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
41484181
(ins GPRnopc:$Rn, GPRnopc:$Rm),
41494182
IIC_iMAC64, "smlalbt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4150-
Requires<[IsARM, HasV5TE]>;
4183+
Requires<[IsARM, HasV5TE]>,
4184+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
41514185

41524186
def SMLALTB : AMulxyI64<0b0001010, 0b01, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
41534187
(ins GPRnopc:$Rn, GPRnopc:$Rm),
41544188
IIC_iMAC64, "smlaltb", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4155-
Requires<[IsARM, HasV5TE]>;
4189+
Requires<[IsARM, HasV5TE]>,
4190+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
41564191

41574192
def SMLALTT : AMulxyI64<0b0001010, 0b11, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
41584193
(ins GPRnopc:$Rn, GPRnopc:$Rm),
41594194
IIC_iMAC64, "smlaltt", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
4160-
Requires<[IsARM, HasV5TE]>;
4195+
Requires<[IsARM, HasV5TE]>,
4196+
Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
41614197

41624198
// Helper class for AI_smld.
41634199
class AMulDualIbase<bit long, bit sub, bit swap, dag oops, dag iops,
@@ -4203,19 +4239,23 @@ multiclass AI_smld<bit sub, string opc> {
42034239

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def D : AMulDualIa<0, sub, 0, (outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4206-
NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">;
4242+
NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm, $Ra">,
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Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
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def DX: AMulDualIa<0, sub, 1, (outs GPRnopc:$Rd),
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(ins GPRnopc:$Rn, GPRnopc:$Rm, GPR:$Ra),
4210-
NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">;
4247+
NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm, $Ra">,
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Sched<[WriteMAC32, ReadMUL, ReadMUL, ReadMAC]>;
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def LD: AMulDualI64<1, sub, 0, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
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(ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4214-
!strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">;
4252+
!strconcat(opc, "ld"), "\t$RdLo, $RdHi, $Rn, $Rm">,
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Sched<[WriteMAC64Lo, WriteMAC64Hi, ReadMUL, ReadMUL, ReadMAC, ReadMAC]>;
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def LDX : AMulDualI64<1, sub, 1, (outs GPRnopc:$RdLo, GPRnopc:$RdHi),
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(ins GPRnopc:$Rn, GPRnopc:$Rm), NoItinerary,
4218-
!strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">;
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!strconcat(opc, "ldx"),"\t$RdLo, $RdHi, $Rn, $Rm">,
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Sched<[WriteMUL64Lo, WriteMUL64Hi, ReadMUL, ReadMUL]>;
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}
42214261

@@ -4225,9 +4265,11 @@ defm SMLS : AI_smld<1, "smls">;
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multiclass AI_sdml<bit sub, string opc> {
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def D:AMulDualI<0, sub, 0, (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, GPRnopc:$Rm),
4228-
NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">;
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NoItinerary, !strconcat(opc, "d"), "\t$Rd, $Rn, $Rm">,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
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def DX:AMulDualI<0, sub, 1, (outs GPRnopc:$Rd),(ins GPRnopc:$Rn, GPRnopc:$Rm),
4230-
NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">;
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NoItinerary, !strconcat(opc, "dx"), "\t$Rd, $Rn, $Rm">,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
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}
42324274

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defm SMUA : AI_sdml<0, "smua">;
@@ -4239,12 +4281,14 @@ defm SMUS : AI_sdml<1, "smus">;
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def SDIV : ADivA1I<0b001, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
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"sdiv", "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (sdiv GPR:$Rn, GPR:$Rm))]>,
4242-
Requires<[IsARM, HasDivideInARM]>;
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Requires<[IsARM, HasDivideInARM]>,
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Sched<[WriteDIV]>;
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def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
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"udiv", "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, (udiv GPR:$Rn, GPR:$Rm))]>,
4247-
Requires<[IsARM, HasDivideInARM]>;
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Requires<[IsARM, HasDivideInARM]>,
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Sched<[WriteDIV]>;
42484292

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//===----------------------------------------------------------------------===//
42504294
// Misc. Arithmetic Instructions.
@@ -5526,20 +5570,26 @@ def : ARMPat<(extloadi16 addrmodepc:$addr), (PICLDRH addrmodepc:$addr)>;
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// smul* and smla*
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def : ARMV5TEPat<(mul sext_16_node:$a, sext_16_node:$b),
5529-
(SMULBB GPR:$a, GPR:$b)>;
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(SMULBB GPR:$a, GPR:$b)>,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
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def : ARMV5TEPat<(mul sext_16_node:$a, (sra GPR:$b, (i32 16))),
5531-
(SMULBT GPR:$a, GPR:$b)>;
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(SMULBT GPR:$a, GPR:$b)>,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
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def : ARMV5TEPat<(mul (sra GPR:$a, (i32 16)), sext_16_node:$b),
5533-
(SMULTB GPR:$a, GPR:$b)>;
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(SMULTB GPR:$a, GPR:$b)>,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
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def : ARMV5MOPat<(add GPR:$acc,
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(mul sext_16_node:$a, sext_16_node:$b)),
5536-
(SMLABB GPR:$a, GPR:$b, GPR:$acc)>;
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(SMLABB GPR:$a, GPR:$b, GPR:$acc)>,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
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def : ARMV5MOPat<(add GPR:$acc,
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(mul sext_16_node:$a, (sra GPR:$b, (i32 16)))),
5539-
(SMLABT GPR:$a, GPR:$b, GPR:$acc)>;
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(SMLABT GPR:$a, GPR:$b, GPR:$acc)>,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
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def : ARMV5MOPat<(add GPR:$acc,
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(mul (sra GPR:$a, (i32 16)), sext_16_node:$b)),
5542-
(SMLATB GPR:$a, GPR:$b, GPR:$acc)>;
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(SMLATB GPR:$a, GPR:$b, GPR:$acc)>,
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Sched<[WriteMUL32, ReadMUL, ReadMUL]>;
55435593

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// Pre-v7 uses MCR for synchronization barriers.
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def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,

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