style changes, small fix

Author: mihajlovicana

llvm/lib/Target/AMDGPU/AMDGPUWaitSGPRHazards.cpp

@@ -190,19 +190,18 @@ class AMDGPUWaitSGPRHazards {
     return Mask;
   }
 
-  bool mergeSubsequentWaitAlus(MachineBasicBlock::instr_iterator &MI,
-                               unsigned Mask) {
+  bool mergeConsecutiveWaitAlus(MachineBasicBlock::instr_iterator &MI,
+                                unsigned Mask) {
     auto MBB = MI->getParent();
-    if (MI != MBB->instr_begin()) {
-      MachineBasicBlock::instr_iterator It = std::prev(MI);
-      while (It != MBB->instr_begin() && It->isDebugInstr())
-        --It;
-      if (It->getOpcode() == AMDGPU::S_WAITCNT_DEPCTR) {
-        It->getOperand(0).setImm(mergeMasks(Mask, It->getOperand(0).getImm()));
-        return true;
-      }
-    }
-    return false;
+    if (MI == MBB->instr_begin())
+      return false;
+
+    auto It = prev_nodbg(MI, MBB->instr_begin());
+    if (It->getOpcode() != AMDGPU::S_WAITCNT_DEPCTR)
+      return false;
+
+    It->getOperand(0).setImm(mergeMasks(Mask, It->getOperand(0).getImm()));
+    return true;
   }
 
   bool runOnMachineBasicBlock(MachineBasicBlock &MBB, bool Emit) {
@@ -403,7 +402,7 @@ class AMDGPUWaitSGPRHazards {
           Mask = AMDGPU::DepCtr::encodeFieldVaSdst(Mask, 0);
         }
         if (Emit) {
-          if (!mergeSubsequentWaitAlus(MI, Mask)) {
+          if (!mergeConsecutiveWaitAlus(MI, Mask)) {
             auto NewMI = BuildMI(MBB, MI, MI->getDebugLoc(),
                                  TII->get(AMDGPU::S_WAITCNT_DEPCTR))
                              .addImm(Mask);

llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

@@ -1805,15 +1805,15 @@ unsigned encodeFieldVaSsrc(unsigned Encoded, unsigned VaSsrc) {
 }
 
 unsigned encodeFieldVaSsrc(unsigned VaSsrc) {
-  return encodeFieldVaSsrc(0xfff, VaSsrc);
+  return encodeFieldVaSsrc(0xffff, VaSsrc);
 }
 
 unsigned encodeFieldHoldCnt(unsigned Encoded, unsigned HoldCnt) {
   return packBits(HoldCnt, Encoded, getHoldCntBitShift(), getHoldCntWidth());
 }
 
 unsigned encodeFieldHoldCnt(unsigned HoldCnt) {
-  return encodeFieldHoldCnt(0xfff, HoldCnt);
+  return encodeFieldHoldCnt(0xffff, HoldCnt);
 }
 
 } // namespace DepCtr

llvm/test/CodeGen/AMDGPU/merge-consecutive-wait-alus.mir

@@ -76,3 +76,4 @@ body: |
     DBG_VALUE $sgpr0
     renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, killed $vgpr0, killed $sgpr0, implicit $exec, implicit-def $vcc
 ...
+