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1 parent 2176af7 commit bbe6c81Copy full SHA for bbe6c81
llvm/test/CodeGen/RISCV/sifive7-enable-intervals.mir
@@ -1,6 +1,7 @@
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# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=machine-scheduler \
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# RUN: -debug-only=machine-scheduler -misched-dump-schedule-trace \
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# RUN: -misched-topdown -o - %s 2>&1 | FileCheck %s
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+# REQUIRES: asserts
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# The purpose of this test is to show that the VADD instructions are issued so
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# that the SiFive7VA is saturated.
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