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[RISCV] Support codegen of vfmv.v.f for bfloat vector with both Zvfbfmin and Zfbfmin (#87318)
vfmv, vfmerge should support bfloat vector when we have both Zvfbfmin and Zfbfmin, this patch tries to support vfmv first.
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-4
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4 files changed

+135
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‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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Original file line numberDiff line numberDiff line change
@@ -761,6 +761,11 @@ class GetVTypePredicates<VTypeInfo vti> {
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true : [HasVInstructions]);
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}
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class GetVTypeScalarPredicates<VTypeInfo vti> {
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list<Predicate> Predicates = !cond(!eq(vti.Scalar, bf16) : [HasStdExtZfbfmin],
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true : []);
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}
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class VPseudoUSLoadNoMask<VReg RetClass,
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int EEW> :
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Pseudo<(outs RetClass:$rd),

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

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@@ -1454,8 +1454,9 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
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// Vector Splats
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//===----------------------------------------------------------------------===//
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foreach fvti = AllFloatVectors in {
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let Predicates = GetVTypePredicates<fvti>.Predicates in
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foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in {
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let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
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GetVTypeScalarPredicates<fvti>.Predicates) in
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def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl undef, fvti.ScalarRegClass:$rs1, srcvalue)),
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(!cast<Instruction>("PseudoVFMV_V_"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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(fvti.Vector (IMPLICIT_DEF)),

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

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@@ -2599,7 +2599,12 @@ foreach fvti = AllFloatVectors in {
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fvti.RegClass:$merge, fvti.RegClass:$rs2,
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(fvti.Scalar fvti.ScalarRegClass:$rs1),
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(fvti.Mask V0), GPR:$vl, fvti.Log2SEW)>;
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}
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}
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foreach fvti = !listconcat(AllFloatVectors, AllBFloatVectors) in {
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let Predicates = !listconcat(GetVTypePredicates<fvti>.Predicates,
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GetVTypeScalarPredicates<fvti>.Predicates) in {
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// 13.16. Vector Floating-Point Move Instruction
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// If we're splatting fpimm0, use vmv.v.x vd, x0.
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def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl

‎llvm/test/CodeGen/RISCV/rvv/vfmv.v.f.ll

Lines changed: 122 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh \
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin \
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; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh \
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+zvfh,+experimental-zfbfmin,+experimental-zvfbfmin \
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; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
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declare <vscale x 1 x half> @llvm.riscv.vfmv.v.f.nxv1f16(
@@ -528,3 +528,123 @@ entry:
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ret <vscale x 8 x double> %a
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}
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declare <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16(
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<vscale x 1 x bfloat>,
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bfloat,
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iXLen);
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define <vscale x 1 x bfloat> @intrinsic_vfmv.v.f_f_nxv1bf16(bfloat %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv1bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
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; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x bfloat> @llvm.riscv.vfmv.v.f.nxv1bf16(
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<vscale x 1 x bfloat> undef,
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bfloat %0,
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iXLen %1)
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ret <vscale x 1 x bfloat> %a
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}
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declare <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16(
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<vscale x 2 x bfloat>,
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bfloat,
555+
iXLen);
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define <vscale x 2 x bfloat> @intrinsic_vfmv.v.f_f_nxv2bf16(bfloat %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv2bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
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; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x bfloat> @llvm.riscv.vfmv.v.f.nxv2bf16(
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<vscale x 2 x bfloat> undef,
566+
bfloat %0,
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iXLen %1)
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569+
ret <vscale x 2 x bfloat> %a
570+
}
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declare <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16(
573+
<vscale x 4 x bfloat>,
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bfloat,
575+
iXLen);
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577+
define <vscale x 4 x bfloat> @intrinsic_vfmv.v.f_f_nxv4bf16(bfloat %0, iXLen %1) nounwind {
578+
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv4bf16:
579+
; CHECK: # %bb.0: # %entry
580+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: ret
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entry:
584+
%a = call <vscale x 4 x bfloat> @llvm.riscv.vfmv.v.f.nxv4bf16(
585+
<vscale x 4 x bfloat> undef,
586+
bfloat %0,
587+
iXLen %1)
588+
589+
ret <vscale x 4 x bfloat> %a
590+
}
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592+
declare <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16(
593+
<vscale x 8 x bfloat>,
594+
bfloat,
595+
iXLen);
596+
597+
define <vscale x 8 x bfloat> @intrinsic_vfmv.v.f_f_nxv8bf16(bfloat %0, iXLen %1) nounwind {
598+
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv8bf16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
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; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: ret
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entry:
604+
%a = call <vscale x 8 x bfloat> @llvm.riscv.vfmv.v.f.nxv8bf16(
605+
<vscale x 8 x bfloat> undef,
606+
bfloat %0,
607+
iXLen %1)
608+
609+
ret <vscale x 8 x bfloat> %a
610+
}
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612+
declare <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16(
613+
<vscale x 16 x bfloat>,
614+
bfloat,
615+
iXLen);
616+
617+
define <vscale x 16 x bfloat> @intrinsic_vfmv.v.f_f_nxv16bf16(bfloat %0, iXLen %1) nounwind {
618+
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv16bf16:
619+
; CHECK: # %bb.0: # %entry
620+
; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
621+
; CHECK-NEXT: vfmv.v.f v8, fa0
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; CHECK-NEXT: ret
623+
entry:
624+
%a = call <vscale x 16 x bfloat> @llvm.riscv.vfmv.v.f.nxv16bf16(
625+
<vscale x 16 x bfloat> undef,
626+
bfloat %0,
627+
iXLen %1)
628+
629+
ret <vscale x 16 x bfloat> %a
630+
}
631+
632+
declare <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16(
633+
<vscale x 32 x bfloat>,
634+
bfloat,
635+
iXLen);
636+
637+
define <vscale x 32 x bfloat> @intrinsic_vfmv.v.f_f_nxv32bf16(bfloat %0, iXLen %1) nounwind {
638+
; CHECK-LABEL: intrinsic_vfmv.v.f_f_nxv32bf16:
639+
; CHECK: # %bb.0: # %entry
640+
; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
641+
; CHECK-NEXT: vfmv.v.f v8, fa0
642+
; CHECK-NEXT: ret
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entry:
644+
%a = call <vscale x 32 x bfloat> @llvm.riscv.vfmv.v.f.nxv32bf16(
645+
<vscale x 32 x bfloat> undef,
646+
bfloat %0,
647+
iXLen %1)
648+
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ret <vscale x 32 x bfloat> %a
650+
}

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