changed trunc pattern in oneuse

Author: mihajlovicana

llvm/lib/Target/AMDGPU/SIInstructions.td

@@ -3124,12 +3124,12 @@ def IMMBitSelConst : SDNodeXForm<imm, [{
 
 // Handle the VALU case.
 def : GCNPat <
-  (i1 (xor (i1 (DivergentUnaryFrag<trunc> i32:$a)), -1)),
+  (i1 (xor (i1 (DivergentUnaryFrag_oneuse<trunc> i32:$a)), -1)),
   (V_CMP_NE_U32_e64 (V_AND_B32_e64 (i32 1), i32:$a), (i32 1))
 >;
 
 def : GCNPat <
-  (i1 (xor (i1 (DivergentUnaryFrag<trunc> i64:$a)), -1)),
+  (i1 (xor (i1 (DivergentUnaryFrag_oneuse<trunc> i64:$a)), -1)),
   (V_CMP_NE_U32_e64 (V_AND_B32_e64 (i32 1),
   (i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
 >;

llvm/lib/Target/AMDGPU/VOPInstructions.td

@@ -1267,6 +1267,19 @@ class DivergentUnaryFrag<SDPatternOperator Op> : PatFrag <
   let GISelPredicateCode = [{return true;}];
 }
 
+class DivergentUnaryFrag_oneuse<SDPatternOperator Op> : PatFrag <
+  (ops node:$src0),
+  (Op $src0),
+  [{ return N->isDivergent(); }]> {
+  // This check is unnecessary as it's captured by the result register
+  // bank constraint.
+  //
+  // FIXME: Should add a way for the emitter to recognize this is a
+  // trivially true predicate to eliminate the check.
+  let GISelPredicateCode = [{return true;}];
+  let HasOneUse = 1;
+}
+
 class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> {
   list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []);
 }

llvm/test/CodeGen/AMDGPU/codegen-prepare-addrspacecast-non-null.ll

@@ -207,22 +207,22 @@ define void @recursive_phis(i1 %cond, ptr addrspace(5) %ptr) {
 ; DAGISEL-ASM:       ; %bb.0: ; %entry
 ; DAGISEL-ASM-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; DAGISEL-ASM-NEXT:    v_and_b32_e32 v0, 1, v0
-; DAGISEL-ASM-NEXT:    v_cmp_eq_u32_e64 s[4:5], 1, v0
-; DAGISEL-ASM-NEXT:    v_cmp_ne_u32_e32 vcc, 1, v0
+; DAGISEL-ASM-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
 ; DAGISEL-ASM-NEXT:    v_lshrrev_b32_e64 v0, 6, s32
-; DAGISEL-ASM-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
+; DAGISEL-ASM-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; DAGISEL-ASM-NEXT:  ; %bb.1: ; %then
 ; DAGISEL-ASM-NEXT:    v_and_b32_e32 v0, 0xffff, v1
 ; DAGISEL-ASM-NEXT:  ; %bb.2: ; %finallyendcf.split
-; DAGISEL-ASM-NEXT:    s_or_b64 exec, exec, s[6:7]
+; DAGISEL-ASM-NEXT:    s_or_b64 exec, exec, s[4:5]
+; DAGISEL-ASM-NEXT:    s_xor_b64 s[6:7], vcc, -1
 ; DAGISEL-ASM-NEXT:    s_mov_b64 s[4:5], 0
-; DAGISEL-ASM-NEXT:    s_mov_b64 s[6:7], src_private_base
+; DAGISEL-ASM-NEXT:    s_mov_b64 s[8:9], src_private_base
 ; DAGISEL-ASM-NEXT:    v_mov_b32_e32 v2, 7
 ; DAGISEL-ASM-NEXT:  .LBB7_3: ; %finally
 ; DAGISEL-ASM-NEXT:    ; =>This Inner Loop Header: Depth=1
-; DAGISEL-ASM-NEXT:    s_and_b64 s[8:9], exec, vcc
-; DAGISEL-ASM-NEXT:    s_or_b64 s[4:5], s[8:9], s[4:5]
-; DAGISEL-ASM-NEXT:    v_mov_b32_e32 v1, s7
+; DAGISEL-ASM-NEXT:    s_and_b64 s[10:11], exec, s[6:7]
+; DAGISEL-ASM-NEXT:    s_or_b64 s[4:5], s[10:11], s[4:5]
+; DAGISEL-ASM-NEXT:    v_mov_b32_e32 v1, s9
 ; DAGISEL-ASM-NEXT:    flat_store_dword v[0:1], v2
 ; DAGISEL-ASM-NEXT:    s_waitcnt vmcnt(0)
 ; DAGISEL-ASM-NEXT:    s_andn2_b64 exec, exec, s[4:5]