[RISCV][TTI/SLP] Add test coverage for select of constants costing

Provides coverage for an upcoming change which accounts for the cost
of materializing the vector constants in the vector select.

Author: preames

llvm/test/Analysis/CostModel/RISCV/rvv-select.ll

@@ -390,3 +390,28 @@ define void @select() {
 
   ret void
 }
+
+define void @select_of_constants() {
+; CHECK-LABEL: 'select_of_constants'
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %1 = select i1 undef, <2 x i64> <i64 128, i64 128>, <2 x i64> zeroinitializer
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %2 = select i1 undef, <2 x i64> <i64 128, i64 127>, <2 x i64> zeroinitializer
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %3 = select i1 undef, <2 x i64> <i64 0, i64 1>, <2 x i64> zeroinitializer
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %4 = select i1 undef, <2 x i64> <i64 128, i64 533>, <2 x i64> <i64 0, i64 573>
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %5 = select <4 x i1> undef, <4 x i32> <i32 524288, i32 262144, i32 131072, i32 65536>, <4 x i32> zeroinitializer
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
+;
+  ; Splat constants
+  select i1 undef, <2 x i64> <i64 128, i64 128>, <2 x i64> zeroinitializer
+  ; LHS is a VID patern
+  select i1 undef, <2 x i64> <i64 128, i64 127>, <2 x i64> zeroinitializer
+  select i1 undef, <2 x i64> <i64 0, i64 1>, <2 x i64> zeroinitializer
+  ; 2x general (expensive) constants
+  select i1 undef, <2 x i64> <i64 128, i64 533>, <2 x i64> <i64 0, i64 573>
+
+  ; powers of two (still expensive)
+  select <4 x i1> undef, <4 x i32> <i32 524288, i32 262144, i32 131072, i32 65536>, <4 x i32> zeroinitializer
+
+  ret void
+}
+
+

llvm/test/Transforms/SLPVectorizer/RISCV/select-profitability.ll

@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux -mattr=+v < %s | FileCheck %s
+
+define i32 @pow2_zero_constant_shift(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
+; CHECK-LABEL: define i32 @pow2_zero_constant_shift(
+; CHECK-SAME: i16 zeroext [[A:%.*]], i16 zeroext [[B:%.*]], i16 zeroext [[C:%.*]], i16 zeroext [[D:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[B]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[C]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x i16> [[TMP3]], i16 [[D]], i32 3
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq <4 x i16> [[TMP4]], <i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP6:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> <i32 65536, i32 65536, i32 65536, i32 65536>, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP6]])
+; CHECK-NEXT:    ret i32 [[TMP7]]
+;
+  %t39.i0 = icmp eq i16 %a, 1
+  %t39.i1 = icmp eq i16 %b, 1
+  %t39.i2 = icmp eq i16 %c, 1
+  %t39.i3 = icmp eq i16 %d, 1
+  %t40.i0 = select i1 %t39.i0, i32 65536, i32 0
+  %t40.i1 = select i1 %t39.i1, i32 65536, i32 0
+  %t40.i2 = select i1 %t39.i2, i32 65536, i32 0
+  %t40.i3 = select i1 %t39.i3, i32 65536, i32 0
+  %or.rdx0 = or i32 %t40.i0, %t40.i1
+  %or.rdx1 = or i32 %t40.i2, %t40.i3
+  %or.rdx2 = or i32 %or.rdx0, %or.rdx1
+  ret i32 %or.rdx2
+}
+
+; TODO: This case is unprofitable, and we should not be vectorizing this.
+define i32 @pow2_zero_variable_shift(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
+; CHECK-LABEL: define i32 @pow2_zero_variable_shift(
+; CHECK-SAME: i16 zeroext [[A:%.*]], i16 zeroext [[B:%.*]], i16 zeroext [[C:%.*]], i16 zeroext [[D:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <4 x i16> poison, i16 [[A]], i32 0
+; CHECK-NEXT:    [[TMP2:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[B]], i32 1
+; CHECK-NEXT:    [[TMP3:%.*]] = insertelement <4 x i16> [[TMP2]], i16 [[C]], i32 2
+; CHECK-NEXT:    [[TMP4:%.*]] = insertelement <4 x i16> [[TMP3]], i16 [[D]], i32 3
+; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq <4 x i16> [[TMP4]], <i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT:    [[TMP6:%.*]] = select <4 x i1> [[TMP5]], <4 x i32> <i32 524288, i32 262144, i32 131072, i32 65536>, <4 x i32> zeroinitializer
+; CHECK-NEXT:    [[OR_RDX2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP6]])
+; CHECK-NEXT:    ret i32 [[OR_RDX2]]
+;
+  %t39.i0 = icmp eq i16 %a, 1
+  %t39.i1 = icmp eq i16 %b, 1
+  %t39.i2 = icmp eq i16 %c, 1
+  %t39.i3 = icmp eq i16 %d, 1
+  %t40.i0 = select i1 %t39.i0, i32 524288, i32 0
+  %t40.i1 = select i1 %t39.i1, i32 262144, i32 0
+  %t40.i2 = select i1 %t39.i2, i32 131072, i32 0
+  %t40.i3 = select i1 %t39.i3, i32 65536, i32 0
+  %or.rdx0 = or i32 %t40.i0, %t40.i1
+  %or.rdx1 = or i32 %t40.i2, %t40.i3
+  %or.rdx2 = or i32 %or.rdx0, %or.rdx1
+  ret i32 %or.rdx2
+}