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AMDGPU: Move default wavesize hack for disassembler
You cannot adjust the disassembler's subtarget. llvm-mc passes the originally constructed MCSubtargetInfo around, rather than querying the pointer in the disassembler instance.
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2 files changed

+18
-19
lines changed

2 files changed

+18
-19
lines changed

llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp

Lines changed: 2 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -45,26 +45,10 @@ using namespace llvm;
4545

4646
using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
4747

48-
static const MCSubtargetInfo &addDefaultWaveSize(const MCSubtargetInfo &STI,
49-
MCContext &Ctx) {
50-
if (!STI.hasFeature(AMDGPU::FeatureWavefrontSize64) &&
51-
!STI.hasFeature(AMDGPU::FeatureWavefrontSize32)) {
52-
MCSubtargetInfo &STICopy = Ctx.getSubtargetCopy(STI);
53-
// If there is no default wave size it must be a generation before gfx10,
54-
// these have FeatureWavefrontSize64 in their definition already. For gfx10+
55-
// set wave32 as a default.
56-
STICopy.ToggleFeature(AMDGPU::FeatureWavefrontSize32);
57-
return STICopy;
58-
}
59-
60-
return STI;
61-
}
62-
6348
AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
6449
MCContext &Ctx, MCInstrInfo const *MCII)
65-
: MCDisassembler(addDefaultWaveSize(STI, Ctx), Ctx), MCII(MCII),
66-
MRI(*Ctx.getRegisterInfo()), MAI(*Ctx.getAsmInfo()),
67-
TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
50+
: MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
51+
MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)),
6852
CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) {
6953
// ToDo: AMDGPUDisassembler supports only VI ISA.
7054
if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus())

llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp

Lines changed: 16 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,22 @@ static MCSubtargetInfo *
7777
createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
7878
if (TT.getArch() == Triple::r600)
7979
return createR600MCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
80-
return createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
80+
81+
MCSubtargetInfo *STI =
82+
createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
83+
84+
// FIXME: We should error for the default target.
85+
if (!STI->hasFeature(AMDGPU::FeatureWavefrontSize64) &&
86+
!STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) {
87+
// If there is no default wave size it must be a generation before gfx10,
88+
// these have FeatureWavefrontSize64 in their definition already. For gfx10+
89+
// set wave32 as a default.
90+
STI->ToggleFeature(AMDGPU::isGFX10Plus(*STI)
91+
? AMDGPU::FeatureWavefrontSize32
92+
: AMDGPU::FeatureWavefrontSize64);
93+
}
94+
95+
return STI;
8196
}
8297

8398
static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,

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