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[X86] Rename VPERMI2/VPERMT2 to VPERMI2*Z/VPERMT2*Z (#75192)
Add missing AVX512 Z prefix to conform to the standard naming convention and simplify matching in X86FoldTablesEmitter::addBroadcastEntry etc.
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8 files changed

+370
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‎llvm/lib/Target/X86/X86InstrAVX512.td

Lines changed: 39 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -1624,19 +1624,19 @@ multiclass avx512_perm_i_sizes<bits<8> opc, string OpcodeStr,
16241624
X86FoldableSchedWrite sched,
16251625
AVX512VLVectorVTInfo VTInfo,
16261626
AVX512VLVectorVTInfo ShuffleMask> {
1627-
defm NAME: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
1628-
ShuffleMask.info512>,
1629-
avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info512,
1630-
ShuffleMask.info512>, EVEX_V512;
1627+
defm NAME#Z: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
1628+
ShuffleMask.info512>,
1629+
avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info512,
1630+
ShuffleMask.info512>, EVEX_V512;
16311631
let Predicates = [HasVLX] in {
1632-
defm NAME#128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
1633-
ShuffleMask.info128>,
1634-
avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info128,
1635-
ShuffleMask.info128>, EVEX_V128;
1636-
defm NAME#256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
1637-
ShuffleMask.info256>,
1638-
avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info256,
1639-
ShuffleMask.info256>, EVEX_V256;
1632+
defm NAME#Z128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
1633+
ShuffleMask.info128>,
1634+
avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info128,
1635+
ShuffleMask.info128>, EVEX_V128;
1636+
defm NAME#Z256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
1637+
ShuffleMask.info256>,
1638+
avx512_perm_i_mb<opc, OpcodeStr, sched, VTInfo.info256,
1639+
ShuffleMask.info256>, EVEX_V256;
16401640
}
16411641
}
16421642

@@ -1646,13 +1646,13 @@ multiclass avx512_perm_i_sizes_bw<bits<8> opc, string OpcodeStr,
16461646
AVX512VLVectorVTInfo Idx,
16471647
Predicate Prd> {
16481648
let Predicates = [Prd] in
1649-
defm NAME: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
1650-
Idx.info512>, EVEX_V512;
1649+
defm NAME#Z: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info512,
1650+
Idx.info512>, EVEX_V512;
16511651
let Predicates = [Prd, HasVLX] in {
1652-
defm NAME#128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
1653-
Idx.info128>, EVEX_V128;
1654-
defm NAME#256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
1655-
Idx.info256>, EVEX_V256;
1652+
defm NAME#Z128: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info128,
1653+
Idx.info128>, EVEX_V128;
1654+
defm NAME#Z256: avx512_perm_i<opc, OpcodeStr, sched, VTInfo.info256,
1655+
Idx.info256>, EVEX_V256;
16561656
}
16571657
}
16581658

@@ -1702,9 +1702,9 @@ multiclass avx512_perm_i_lowering<string InstrStr, X86VectorVTInfo _,
17021702
}
17031703

17041704
// TODO: Should we add more casts? The vXi64 case is common due to ABI.
1705-
defm : avx512_perm_i_lowering<"VPERMI2PS", v16f32_info, v16i32_info, v8i64_info>;
1706-
defm : avx512_perm_i_lowering<"VPERMI2PS256", v8f32x_info, v8i32x_info, v4i64x_info>;
1707-
defm : avx512_perm_i_lowering<"VPERMI2PS128", v4f32x_info, v4i32x_info, v2i64x_info>;
1705+
defm : avx512_perm_i_lowering<"VPERMI2PSZ", v16f32_info, v16i32_info, v8i64_info>;
1706+
defm : avx512_perm_i_lowering<"VPERMI2PSZ256", v8f32x_info, v8i32x_info, v4i64x_info>;
1707+
defm : avx512_perm_i_lowering<"VPERMI2PSZ128", v4f32x_info, v4i32x_info, v2i64x_info>;
17081708

17091709
// VPERMT2
17101710
multiclass avx512_perm_t<bits<8> opc, string OpcodeStr,
@@ -1743,19 +1743,19 @@ multiclass avx512_perm_t_sizes<bits<8> opc, string OpcodeStr,
17431743
X86FoldableSchedWrite sched,
17441744
AVX512VLVectorVTInfo VTInfo,
17451745
AVX512VLVectorVTInfo ShuffleMask> {
1746-
defm NAME: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
1747-
ShuffleMask.info512>,
1748-
avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info512,
1749-
ShuffleMask.info512>, EVEX_V512;
1746+
defm NAME#Z: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
1747+
ShuffleMask.info512>,
1748+
avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info512,
1749+
ShuffleMask.info512>, EVEX_V512;
17501750
let Predicates = [HasVLX] in {
1751-
defm NAME#128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
1752-
ShuffleMask.info128>,
1753-
avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info128,
1754-
ShuffleMask.info128>, EVEX_V128;
1755-
defm NAME#256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
1756-
ShuffleMask.info256>,
1757-
avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info256,
1758-
ShuffleMask.info256>, EVEX_V256;
1751+
defm NAME#Z128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
1752+
ShuffleMask.info128>,
1753+
avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info128,
1754+
ShuffleMask.info128>, EVEX_V128;
1755+
defm NAME#Z256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
1756+
ShuffleMask.info256>,
1757+
avx512_perm_t_mb<opc, OpcodeStr, sched, VTInfo.info256,
1758+
ShuffleMask.info256>, EVEX_V256;
17591759
}
17601760
}
17611761

@@ -1764,13 +1764,13 @@ multiclass avx512_perm_t_sizes_bw<bits<8> opc, string OpcodeStr,
17641764
AVX512VLVectorVTInfo VTInfo,
17651765
AVX512VLVectorVTInfo Idx, Predicate Prd> {
17661766
let Predicates = [Prd] in
1767-
defm NAME: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
1768-
Idx.info512>, EVEX_V512;
1767+
defm NAME#Z: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info512,
1768+
Idx.info512>, EVEX_V512;
17691769
let Predicates = [Prd, HasVLX] in {
1770-
defm NAME#128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
1771-
Idx.info128>, EVEX_V128;
1772-
defm NAME#256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
1773-
Idx.info256>, EVEX_V256;
1770+
defm NAME#Z128: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info128,
1771+
Idx.info128>, EVEX_V128;
1772+
defm NAME#Z256: avx512_perm_t<opc, OpcodeStr, sched, VTInfo.info256,
1773+
Idx.info256>, EVEX_V256;
17741774
}
17751775
}
17761776

‎llvm/lib/Target/X86/X86InstrInfo.cpp

Lines changed: 72 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -2138,45 +2138,45 @@ static void commuteVPTERNLOG(MachineInstr &MI, unsigned SrcOpIdx1,
21382138
// commuted.
21392139
static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
21402140
#define VPERM_CASES(Suffix) \
2141-
case X86::VPERMI2##Suffix##128rr: \
2142-
case X86::VPERMT2##Suffix##128rr: \
2143-
case X86::VPERMI2##Suffix##256rr: \
2144-
case X86::VPERMT2##Suffix##256rr: \
2145-
case X86::VPERMI2##Suffix##rr: \
2146-
case X86::VPERMT2##Suffix##rr: \
2147-
case X86::VPERMI2##Suffix##128rm: \
2148-
case X86::VPERMT2##Suffix##128rm: \
2149-
case X86::VPERMI2##Suffix##256rm: \
2150-
case X86::VPERMT2##Suffix##256rm: \
2151-
case X86::VPERMI2##Suffix##rm: \
2152-
case X86::VPERMT2##Suffix##rm: \
2153-
case X86::VPERMI2##Suffix##128rrkz: \
2154-
case X86::VPERMT2##Suffix##128rrkz: \
2155-
case X86::VPERMI2##Suffix##256rrkz: \
2156-
case X86::VPERMT2##Suffix##256rrkz: \
2157-
case X86::VPERMI2##Suffix##rrkz: \
2158-
case X86::VPERMT2##Suffix##rrkz: \
2159-
case X86::VPERMI2##Suffix##128rmkz: \
2160-
case X86::VPERMT2##Suffix##128rmkz: \
2161-
case X86::VPERMI2##Suffix##256rmkz: \
2162-
case X86::VPERMT2##Suffix##256rmkz: \
2163-
case X86::VPERMI2##Suffix##rmkz: \
2164-
case X86::VPERMT2##Suffix##rmkz:
2141+
case X86::VPERMI2##Suffix##Z128rr: \
2142+
case X86::VPERMT2##Suffix##Z128rr: \
2143+
case X86::VPERMI2##Suffix##Z256rr: \
2144+
case X86::VPERMT2##Suffix##Z256rr: \
2145+
case X86::VPERMI2##Suffix##Zrr: \
2146+
case X86::VPERMT2##Suffix##Zrr: \
2147+
case X86::VPERMI2##Suffix##Z128rm: \
2148+
case X86::VPERMT2##Suffix##Z128rm: \
2149+
case X86::VPERMI2##Suffix##Z256rm: \
2150+
case X86::VPERMT2##Suffix##Z256rm: \
2151+
case X86::VPERMI2##Suffix##Zrm: \
2152+
case X86::VPERMT2##Suffix##Zrm: \
2153+
case X86::VPERMI2##Suffix##Z128rrkz: \
2154+
case X86::VPERMT2##Suffix##Z128rrkz: \
2155+
case X86::VPERMI2##Suffix##Z256rrkz: \
2156+
case X86::VPERMT2##Suffix##Z256rrkz: \
2157+
case X86::VPERMI2##Suffix##Zrrkz: \
2158+
case X86::VPERMT2##Suffix##Zrrkz: \
2159+
case X86::VPERMI2##Suffix##Z128rmkz: \
2160+
case X86::VPERMT2##Suffix##Z128rmkz: \
2161+
case X86::VPERMI2##Suffix##Z256rmkz: \
2162+
case X86::VPERMT2##Suffix##Z256rmkz: \
2163+
case X86::VPERMI2##Suffix##Zrmkz: \
2164+
case X86::VPERMT2##Suffix##Zrmkz:
21652165

21662166
#define VPERM_CASES_BROADCAST(Suffix) \
21672167
VPERM_CASES(Suffix) \
2168-
case X86::VPERMI2##Suffix##128rmb: \
2169-
case X86::VPERMT2##Suffix##128rmb: \
2170-
case X86::VPERMI2##Suffix##256rmb: \
2171-
case X86::VPERMT2##Suffix##256rmb: \
2172-
case X86::VPERMI2##Suffix##rmb: \
2173-
case X86::VPERMT2##Suffix##rmb: \
2174-
case X86::VPERMI2##Suffix##128rmbkz: \
2175-
case X86::VPERMT2##Suffix##128rmbkz: \
2176-
case X86::VPERMI2##Suffix##256rmbkz: \
2177-
case X86::VPERMT2##Suffix##256rmbkz: \
2178-
case X86::VPERMI2##Suffix##rmbkz: \
2179-
case X86::VPERMT2##Suffix##rmbkz:
2168+
case X86::VPERMI2##Suffix##Z128rmb: \
2169+
case X86::VPERMT2##Suffix##Z128rmb: \
2170+
case X86::VPERMI2##Suffix##Z256rmb: \
2171+
case X86::VPERMT2##Suffix##Z256rmb: \
2172+
case X86::VPERMI2##Suffix##Zrmb: \
2173+
case X86::VPERMT2##Suffix##Zrmb: \
2174+
case X86::VPERMI2##Suffix##Z128rmbkz: \
2175+
case X86::VPERMT2##Suffix##Z128rmbkz: \
2176+
case X86::VPERMI2##Suffix##Z256rmbkz: \
2177+
case X86::VPERMT2##Suffix##Z256rmbkz: \
2178+
case X86::VPERMI2##Suffix##Zrmbkz: \
2179+
case X86::VPERMT2##Suffix##Zrmbkz:
21802180

21812181
switch (Opcode) {
21822182
default:
@@ -2197,45 +2197,45 @@ static bool isCommutableVPERMV3Instruction(unsigned Opcode) {
21972197
// from the I opcode to the T opcode and vice versa.
21982198
static unsigned getCommutedVPERMV3Opcode(unsigned Opcode) {
21992199
#define VPERM_CASES(Orig, New) \
2200-
case X86::Orig##128rr: \
2201-
return X86::New##128rr; \
2202-
case X86::Orig##128rrkz: \
2203-
return X86::New##128rrkz; \
2204-
case X86::Orig##128rm: \
2205-
return X86::New##128rm; \
2206-
case X86::Orig##128rmkz: \
2207-
return X86::New##128rmkz; \
2208-
case X86::Orig##256rr: \
2209-
return X86::New##256rr; \
2210-
case X86::Orig##256rrkz: \
2211-
return X86::New##256rrkz; \
2212-
case X86::Orig##256rm: \
2213-
return X86::New##256rm; \
2214-
case X86::Orig##256rmkz: \
2215-
return X86::New##256rmkz; \
2216-
case X86::Orig##rr: \
2217-
return X86::New##rr; \
2218-
case X86::Orig##rrkz: \
2219-
return X86::New##rrkz; \
2220-
case X86::Orig##rm: \
2221-
return X86::New##rm; \
2222-
case X86::Orig##rmkz: \
2223-
return X86::New##rmkz;
2200+
case X86::Orig##Z128rr: \
2201+
return X86::New##Z128rr; \
2202+
case X86::Orig##Z128rrkz: \
2203+
return X86::New##Z128rrkz; \
2204+
case X86::Orig##Z128rm: \
2205+
return X86::New##Z128rm; \
2206+
case X86::Orig##Z128rmkz: \
2207+
return X86::New##Z128rmkz; \
2208+
case X86::Orig##Z256rr: \
2209+
return X86::New##Z256rr; \
2210+
case X86::Orig##Z256rrkz: \
2211+
return X86::New##Z256rrkz; \
2212+
case X86::Orig##Z256rm: \
2213+
return X86::New##Z256rm; \
2214+
case X86::Orig##Z256rmkz: \
2215+
return X86::New##Z256rmkz; \
2216+
case X86::Orig##Zrr: \
2217+
return X86::New##Zrr; \
2218+
case X86::Orig##Zrrkz: \
2219+
return X86::New##Zrrkz; \
2220+
case X86::Orig##Zrm: \
2221+
return X86::New##Zrm; \
2222+
case X86::Orig##Zrmkz: \
2223+
return X86::New##Zrmkz;
22242224

22252225
#define VPERM_CASES_BROADCAST(Orig, New) \
22262226
VPERM_CASES(Orig, New) \
2227-
case X86::Orig##128rmb: \
2228-
return X86::New##128rmb; \
2229-
case X86::Orig##128rmbkz: \
2230-
return X86::New##128rmbkz; \
2231-
case X86::Orig##256rmb: \
2232-
return X86::New##256rmb; \
2233-
case X86::Orig##256rmbkz: \
2234-
return X86::New##256rmbkz; \
2235-
case X86::Orig##rmb: \
2236-
return X86::New##rmb; \
2237-
case X86::Orig##rmbkz: \
2238-
return X86::New##rmbkz;
2227+
case X86::Orig##Z128rmb: \
2228+
return X86::New##Z128rmb; \
2229+
case X86::Orig##Z128rmbkz: \
2230+
return X86::New##Z128rmbkz; \
2231+
case X86::Orig##Z256rmb: \
2232+
return X86::New##Z256rmb; \
2233+
case X86::Orig##Z256rmbkz: \
2234+
return X86::New##Z256rmbkz; \
2235+
case X86::Orig##Zrmb: \
2236+
return X86::New##Zrmb; \
2237+
case X86::Orig##Zrmbkz: \
2238+
return X86::New##Zrmbkz;
22392239

22402240
switch (Opcode) {
22412241
VPERM_CASES(VPERMI2B, VPERMT2B)

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