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[AMDGPU] Use correct number of bits needed for div/rem shrinking
There was an error where dividend of type i64 and actual used number of bits of 32 fell into path that assumes only 24 bits being used. Check that AtLeast field is used correctly when using computeNumSignBits and add necessary extend/trunc for 32 bits path. Regolden and update testcases.
1 parent 92d5f64 commit bd01b8a

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13 files changed

+997
-886
lines changed

13 files changed

+997
-886
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1213,7 +1213,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder,
12131213
BinaryOperator &I, Value *Num,
12141214
Value *Den, bool IsDiv,
12151215
bool IsSigned) const {
1216-
int DivBits = getDivNumBits(I, Num, Den, 9, IsSigned);
1216+
unsigned SSBits = Num->getType()->getScalarSizeInBits();
1217+
// If Num bits <= 24, assume 0 signbits.
1218+
unsigned AtLeast = (SSBits <= 24) ? 0 : (SSBits - 24);
1219+
int DivBits = getDivNumBits(I, Num, Den, AtLeast, IsSigned);
12171220
if (DivBits == -1)
12181221
return nullptr;
12191222
return expandDivRem24Impl(Builder, I, Num, Den, DivBits, IsDiv, IsSigned);
@@ -1385,13 +1388,13 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder,
13851388
Type *I32Ty = Builder.getInt32Ty();
13861389
Type *F32Ty = Builder.getFloatTy();
13871390

1388-
if (Ty->getScalarSizeInBits() < 32) {
1391+
if (Ty->getScalarSizeInBits() != 32) {
13891392
if (IsSigned) {
1390-
X = Builder.CreateSExt(X, I32Ty);
1391-
Y = Builder.CreateSExt(Y, I32Ty);
1393+
X = Builder.CreateSExtOrTrunc(X, I32Ty);
1394+
Y = Builder.CreateSExtOrTrunc(Y, I32Ty);
13921395
} else {
1393-
X = Builder.CreateZExt(X, I32Ty);
1394-
Y = Builder.CreateZExt(Y, I32Ty);
1396+
X = Builder.CreateZExtOrTrunc(X, I32Ty);
1397+
Y = Builder.CreateZExtOrTrunc(Y, I32Ty);
13951398
}
13961399
}
13971400

@@ -1482,10 +1485,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder,
14821485
if (IsSigned) {
14831486
Res = Builder.CreateXor(Res, Sign);
14841487
Res = Builder.CreateSub(Res, Sign);
1488+
Res = Builder.CreateSExtOrTrunc(Res, Ty);
1489+
} else {
1490+
Res = Builder.CreateZExtOrTrunc(Res, Ty);
14851491
}
1486-
1487-
Res = Builder.CreateTrunc(Res, Ty);
1488-
14891492
return Res;
14901493
}
14911494

‎llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i32.ll

Lines changed: 39 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -741,25 +741,17 @@ define i32 @v_sdiv_i32_24bit(i32 %num, i32 %den) {
741741
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
742742
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
743743
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
744-
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
745-
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
746-
; CGP-NEXT: v_rcp_f32_e32 v2, v2
747-
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
748-
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
749-
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
750-
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
751-
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
752-
; CGP-NEXT: v_mul_hi_u32 v2, v0, v2
753-
; CGP-NEXT: v_mul_lo_u32 v3, v2, v1
754-
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
755-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
756-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
757-
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
758-
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1
759-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
760-
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v2
761-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
762-
; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
744+
; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0
745+
; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1
746+
; CGP-NEXT: v_rcp_f32_e32 v2, v1
747+
; CGP-NEXT: v_mul_f32_e32 v2, v0, v2
748+
; CGP-NEXT: v_trunc_f32_e32 v2, v2
749+
; CGP-NEXT: v_fma_f32 v0, -v2, v1, v0
750+
; CGP-NEXT: v_cvt_i32_f32_e32 v2, v2
751+
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1|
752+
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
753+
; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0
754+
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
763755
; CGP-NEXT: s_setpc_b64 s[30:31]
764756
%num.mask = and i32 %num, 16777215
765757
%den.mask = and i32 %den, 16777215
@@ -840,44 +832,34 @@ define <2 x i32> @v_sdiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {
840832
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
841833
; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
842834
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
843-
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
844-
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
845-
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
846-
; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
847-
; CGP-NEXT: v_rcp_f32_e32 v4, v4
848-
; CGP-NEXT: v_rcp_f32_e32 v6, v6
849-
; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
850-
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
851-
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
852-
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
853-
; CGP-NEXT: v_mul_lo_u32 v5, v5, v4
854-
; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
855-
; CGP-NEXT: v_mul_hi_u32 v5, v4, v5
856-
; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
857-
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
858-
; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7
859-
; CGP-NEXT: v_mul_hi_u32 v4, v0, v4
860-
; CGP-NEXT: v_mul_hi_u32 v5, v1, v5
861-
; CGP-NEXT: v_mul_lo_u32 v6, v4, v2
862-
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4
863-
; CGP-NEXT: v_mul_lo_u32 v8, v5, v3
864-
; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5
865-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
866-
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
867-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
868-
; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
869-
; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2
870-
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3
871-
; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]
872-
; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3
873-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
874-
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4
875-
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]
876-
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5
877-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
878-
; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
879-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
880-
; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
835+
; CGP-NEXT: v_xor_b32_e32 v4, v0, v2
836+
; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0
837+
; CGP-NEXT: v_cvt_f32_i32_e32 v2, v2
838+
; CGP-NEXT: v_xor_b32_e32 v5, v1, v3
839+
; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1
840+
; CGP-NEXT: v_cvt_f32_i32_e32 v3, v3
841+
; CGP-NEXT: v_ashrrev_i32_e32 v4, 30, v4
842+
; CGP-NEXT: v_rcp_f32_e32 v6, v2
843+
; CGP-NEXT: v_ashrrev_i32_e32 v5, 30, v5
844+
; CGP-NEXT: v_rcp_f32_e32 v7, v3
845+
; CGP-NEXT: v_or_b32_e32 v4, 1, v4
846+
; CGP-NEXT: v_mul_f32_e32 v6, v0, v6
847+
; CGP-NEXT: v_or_b32_e32 v5, 1, v5
848+
; CGP-NEXT: v_mul_f32_e32 v7, v1, v7
849+
; CGP-NEXT: v_trunc_f32_e32 v6, v6
850+
; CGP-NEXT: v_trunc_f32_e32 v7, v7
851+
; CGP-NEXT: v_fma_f32 v0, -v6, v2, v0
852+
; CGP-NEXT: v_cvt_i32_f32_e32 v6, v6
853+
; CGP-NEXT: v_fma_f32 v1, -v7, v3, v1
854+
; CGP-NEXT: v_cvt_i32_f32_e32 v7, v7
855+
; CGP-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, |v2|
856+
; CGP-NEXT: v_cndmask_b32_e32 v0, 0, v4, vcc
857+
; CGP-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v3|
858+
; CGP-NEXT: v_cndmask_b32_e32 v1, 0, v5, vcc
859+
; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0
860+
; CGP-NEXT: v_add_i32_e32 v1, vcc, v7, v1
861+
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
862+
; CGP-NEXT: v_bfe_i32 v1, v1, 0, 25
881863
; CGP-NEXT: s_setpc_b64 s[30:31]
882864
%num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>
883865
%den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>

‎llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i32.ll

Lines changed: 45 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -679,23 +679,19 @@ define i32 @v_srem_i32_24bit(i32 %num, i32 %den) {
679679
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
680680
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
681681
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
682-
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
683-
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
684-
; CGP-NEXT: v_rcp_f32_e32 v2, v2
685-
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
686-
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
687-
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
688-
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
689-
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
690-
; CGP-NEXT: v_mul_hi_u32 v2, v0, v2
691-
; CGP-NEXT: v_mul_lo_u32 v2, v2, v1
692-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
693-
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
694-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
695-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
696-
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1
697-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
698-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
682+
; CGP-NEXT: v_cvt_f32_i32_e32 v2, v0
683+
; CGP-NEXT: v_cvt_f32_i32_e32 v3, v1
684+
; CGP-NEXT: v_rcp_f32_e32 v4, v3
685+
; CGP-NEXT: v_mul_f32_e32 v4, v2, v4
686+
; CGP-NEXT: v_trunc_f32_e32 v4, v4
687+
; CGP-NEXT: v_fma_f32 v2, -v4, v3, v2
688+
; CGP-NEXT: v_cvt_i32_f32_e32 v4, v4
689+
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v3|
690+
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
691+
; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2
692+
; CGP-NEXT: v_mul_lo_u32 v1, v2, v1
693+
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
694+
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
699695
; CGP-NEXT: s_setpc_b64 s[30:31]
700696
%num.mask = and i32 %num, 16777215
701697
%den.mask = and i32 %den, 16777215
@@ -770,40 +766,38 @@ define <2 x i32> @v_srem_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {
770766
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
771767
; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
772768
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
773-
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
774-
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
775-
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
776-
; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
777-
; CGP-NEXT: v_rcp_f32_e32 v4, v4
778-
; CGP-NEXT: v_rcp_f32_e32 v6, v6
779-
; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
780-
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
781-
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
782-
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
783-
; CGP-NEXT: v_mul_lo_u32 v5, v5, v4
784-
; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
785-
; CGP-NEXT: v_mul_hi_u32 v5, v4, v5
786-
; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
787-
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
788-
; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7
789-
; CGP-NEXT: v_mul_hi_u32 v4, v0, v4
790-
; CGP-NEXT: v_mul_hi_u32 v5, v1, v5
791-
; CGP-NEXT: v_mul_lo_u32 v4, v4, v2
792-
; CGP-NEXT: v_mul_lo_u32 v5, v5, v3
793-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
794-
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
795-
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
796-
; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3
797-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
798-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
799-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
800-
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
801-
; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
802-
; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3
803-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
804-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
805-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
806-
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
769+
; CGP-NEXT: v_xor_b32_e32 v4, v0, v2
770+
; CGP-NEXT: v_cvt_f32_i32_e32 v5, v0
771+
; CGP-NEXT: v_cvt_f32_i32_e32 v6, v2
772+
; CGP-NEXT: v_xor_b32_e32 v7, v1, v3
773+
; CGP-NEXT: v_cvt_f32_i32_e32 v8, v1
774+
; CGP-NEXT: v_cvt_f32_i32_e32 v9, v3
775+
; CGP-NEXT: v_ashrrev_i32_e32 v4, 30, v4
776+
; CGP-NEXT: v_rcp_f32_e32 v10, v6
777+
; CGP-NEXT: v_ashrrev_i32_e32 v7, 30, v7
778+
; CGP-NEXT: v_rcp_f32_e32 v11, v9
779+
; CGP-NEXT: v_or_b32_e32 v4, 1, v4
780+
; CGP-NEXT: v_mul_f32_e32 v10, v5, v10
781+
; CGP-NEXT: v_or_b32_e32 v7, 1, v7
782+
; CGP-NEXT: v_mul_f32_e32 v11, v8, v11
783+
; CGP-NEXT: v_trunc_f32_e32 v10, v10
784+
; CGP-NEXT: v_trunc_f32_e32 v11, v11
785+
; CGP-NEXT: v_fma_f32 v5, -v10, v6, v5
786+
; CGP-NEXT: v_cvt_i32_f32_e32 v10, v10
787+
; CGP-NEXT: v_fma_f32 v8, -v11, v9, v8
788+
; CGP-NEXT: v_cvt_i32_f32_e32 v11, v11
789+
; CGP-NEXT: v_cmp_ge_f32_e64 vcc, |v5|, |v6|
790+
; CGP-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
791+
; CGP-NEXT: v_cmp_ge_f32_e64 vcc, |v8|, |v9|
792+
; CGP-NEXT: v_cndmask_b32_e32 v5, 0, v7, vcc
793+
; CGP-NEXT: v_add_i32_e32 v4, vcc, v10, v4
794+
; CGP-NEXT: v_add_i32_e32 v5, vcc, v11, v5
795+
; CGP-NEXT: v_mul_lo_u32 v2, v4, v2
796+
; CGP-NEXT: v_mul_lo_u32 v3, v5, v3
797+
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
798+
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
799+
; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25
800+
; CGP-NEXT: v_bfe_i32 v1, v1, 0, 25
807801
; CGP-NEXT: s_setpc_b64 s[30:31]
808802
%num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>
809803
%den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>

‎llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll

Lines changed: 31 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -415,25 +415,17 @@ define i32 @v_udiv_i32_24bit(i32 %num, i32 %den) {
415415
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
416416
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
417417
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
418-
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1
419-
; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1
420-
; CGP-NEXT: v_rcp_f32_e32 v2, v2
421-
; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2
418+
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0
419+
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1
420+
; CGP-NEXT: v_rcp_f32_e32 v2, v1
421+
; CGP-NEXT: v_mul_f32_e32 v2, v0, v2
422+
; CGP-NEXT: v_trunc_f32_e32 v2, v2
423+
; CGP-NEXT: v_fma_f32 v0, -v2, v1, v0
422424
; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2
423-
; CGP-NEXT: v_mul_lo_u32 v3, v3, v2
424-
; CGP-NEXT: v_mul_hi_u32 v3, v2, v3
425-
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3
426-
; CGP-NEXT: v_mul_hi_u32 v2, v0, v2
427-
; CGP-NEXT: v_mul_lo_u32 v3, v2, v1
428-
; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2
429-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
430-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
431-
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
432-
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1
433-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
434-
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v2
435-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1
436-
; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc
425+
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v1
426+
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
427+
; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0
428+
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
437429
; CGP-NEXT: s_setpc_b64 s[30:31]
438430
%num.mask = and i32 %num, 16777215
439431
%den.mask = and i32 %den, 16777215
@@ -496,44 +488,28 @@ define <2 x i32> @v_udiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {
496488
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
497489
; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2
498490
; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3
499-
; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2
500-
; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2
501-
; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3
502-
; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3
503-
; CGP-NEXT: v_rcp_f32_e32 v4, v4
504-
; CGP-NEXT: v_rcp_f32_e32 v6, v6
505-
; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4
506-
; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6
491+
; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0
492+
; CGP-NEXT: v_cvt_f32_u32_e32 v2, v2
493+
; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1
494+
; CGP-NEXT: v_cvt_f32_u32_e32 v3, v3
495+
; CGP-NEXT: v_rcp_f32_e32 v4, v2
496+
; CGP-NEXT: v_rcp_f32_e32 v5, v3
497+
; CGP-NEXT: v_mul_f32_e32 v4, v0, v4
498+
; CGP-NEXT: v_mul_f32_e32 v5, v1, v5
499+
; CGP-NEXT: v_trunc_f32_e32 v4, v4
500+
; CGP-NEXT: v_trunc_f32_e32 v5, v5
501+
; CGP-NEXT: v_fma_f32 v0, -v4, v2, v0
507502
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
508-
; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6
509-
; CGP-NEXT: v_mul_lo_u32 v5, v5, v4
510-
; CGP-NEXT: v_mul_lo_u32 v7, v7, v6
511-
; CGP-NEXT: v_mul_hi_u32 v5, v4, v5
512-
; CGP-NEXT: v_mul_hi_u32 v7, v6, v7
513-
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
514-
; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7
515-
; CGP-NEXT: v_mul_hi_u32 v4, v0, v4
516-
; CGP-NEXT: v_mul_hi_u32 v5, v1, v5
517-
; CGP-NEXT: v_mul_lo_u32 v6, v4, v2
518-
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4
519-
; CGP-NEXT: v_mul_lo_u32 v8, v5, v3
520-
; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5
521-
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
522-
; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
523-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
524-
; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
525-
; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2
526-
; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3
527-
; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]
528-
; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3
529-
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc
530-
; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4
531-
; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]
532-
; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5
533-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2
534-
; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc
535-
; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3
536-
; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc
503+
; CGP-NEXT: v_fma_f32 v1, -v5, v3, v1
504+
; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5
505+
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v2
506+
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
507+
; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, v3
508+
; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
509+
; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0
510+
; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1
511+
; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0
512+
; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1
537513
; CGP-NEXT: s_setpc_b64 s[30:31]
538514
%num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>
539515
%den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>

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