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[RISCV] GISel custom lowering for addiw
Signed-off-by: Luke Quinn <[email protected]>
1 parent cb1ad98 commit bd0a8fb

17 files changed

+183
-119
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@
2121
#include "llvm/CodeGen/MachineConstantPool.h"
2222
#include "llvm/CodeGen/MachineJumpTableInfo.h"
2323
#include "llvm/CodeGen/MachineMemOperand.h"
24+
#include "llvm/CodeGen/MachineOperand.h"
2425
#include "llvm/CodeGen/MachineRegisterInfo.h"
2526
#include "llvm/CodeGen/TargetOpcodes.h"
2627
#include "llvm/CodeGen/ValueTypes.h"
@@ -132,7 +133,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
132133

133134
auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0, nxv16p0};
134135

135-
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
136+
getActionDefinitionsBuilder(G_ADD)
137+
.legalFor({sXLen})
138+
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
139+
.customFor(ST.is64Bit(), {s32})
140+
.widenScalarToNextPow2(0)
141+
.clampScalar(0, sXLen, sXLen);
142+
143+
getActionDefinitionsBuilder({G_SUB, G_AND, G_OR, G_XOR})
136144
.legalFor({sXLen})
137145
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
138146
.widenScalarToNextPow2(0)
@@ -1330,6 +1338,24 @@ bool RISCVLegalizerInfo::legalizeCustom(
13301338
return true;
13311339
return Helper.lowerConstant(MI);
13321340
}
1341+
case TargetOpcode::G_ADD: {
1342+
Helper.Observer.changingInstr(MI);
1343+
Helper.widenScalarSrc(MI, LLT::scalar(64), 1, TargetOpcode::G_ANYEXT);
1344+
Helper.widenScalarSrc(MI, LLT::scalar(64), 2, TargetOpcode::G_ANYEXT);
1345+
1346+
Register DstAdd = MRI.createGenericVirtualRegister(sXLen);
1347+
Register DstSext = MRI.createGenericVirtualRegister(sXLen);
1348+
1349+
MachineOperand &MO = MI.getOperand(0);
1350+
MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1351+
MIRBuilder.buildSExtInReg(DstSext, DstAdd, 32);
1352+
1353+
MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {MO}, {DstSext});
1354+
MO.setReg(DstAdd);
1355+
1356+
Helper.Observer.changedInstr(MI);
1357+
return true;
1358+
}
13331359
case TargetOpcode::G_SEXT_INREG: {
13341360
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
13351361
int64_t SizeInBits = MI.getOperand(2).getImm();

‎llvm/test/CodeGen/RISCV/GlobalISel/add-imm.ll

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ define i32 @add_positive_low_bound_reject(i32 %a) nounwind {
1414
;
1515
; RV64I-LABEL: add_positive_low_bound_reject:
1616
; RV64I: # %bb.0:
17-
; RV64I-NEXT: addi a0, a0, 2047
17+
; RV64I-NEXT: addiw a0, a0, 2047
1818
; RV64I-NEXT: ret
1919
%1 = add i32 %a, 2047
2020
ret i32 %1
@@ -30,7 +30,7 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
3030
; RV64I-LABEL: add_positive_low_bound_accept:
3131
; RV64I: # %bb.0:
3232
; RV64I-NEXT: addi a0, a0, 2047
33-
; RV64I-NEXT: addi a0, a0, 1
33+
; RV64I-NEXT: addiw a0, a0, 1
3434
; RV64I-NEXT: ret
3535
%1 = add i32 %a, 2048
3636
ret i32 %1
@@ -46,7 +46,7 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
4646
; RV64I-LABEL: add_positive_high_bound_accept:
4747
; RV64I: # %bb.0:
4848
; RV64I-NEXT: addi a0, a0, 2047
49-
; RV64I-NEXT: addi a0, a0, 2047
49+
; RV64I-NEXT: addiw a0, a0, 2047
5050
; RV64I-NEXT: ret
5151
%1 = add i32 %a, 4094
5252
ret i32 %1
@@ -63,8 +63,8 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
6363
; RV64I-LABEL: add_positive_high_bound_reject:
6464
; RV64I: # %bb.0:
6565
; RV64I-NEXT: lui a1, 1
66-
; RV64I-NEXT: addiw a1, a1, -1
67-
; RV64I-NEXT: add a0, a0, a1
66+
; RV64I-NEXT: addi a1, a1, -1
67+
; RV64I-NEXT: addw a0, a0, a1
6868
; RV64I-NEXT: ret
6969
%1 = add i32 %a, 4095
7070
ret i32 %1
@@ -78,7 +78,7 @@ define i32 @add_negative_high_bound_reject(i32 %a) nounwind {
7878
;
7979
; RV64I-LABEL: add_negative_high_bound_reject:
8080
; RV64I: # %bb.0:
81-
; RV64I-NEXT: addi a0, a0, -2048
81+
; RV64I-NEXT: addiw a0, a0, -2048
8282
; RV64I-NEXT: ret
8383
%1 = add i32 %a, -2048
8484
ret i32 %1
@@ -94,7 +94,7 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
9494
; RV64I-LABEL: add_negative_high_bound_accept:
9595
; RV64I: # %bb.0:
9696
; RV64I-NEXT: addi a0, a0, -2048
97-
; RV64I-NEXT: addi a0, a0, -1
97+
; RV64I-NEXT: addiw a0, a0, -1
9898
; RV64I-NEXT: ret
9999
%1 = add i32 %a, -2049
100100
ret i32 %1
@@ -110,7 +110,7 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
110110
; RV64I-LABEL: add_negative_low_bound_accept:
111111
; RV64I: # %bb.0:
112112
; RV64I-NEXT: addi a0, a0, -2048
113-
; RV64I-NEXT: addi a0, a0, -2048
113+
; RV64I-NEXT: addiw a0, a0, -2048
114114
; RV64I-NEXT: ret
115115
%1 = add i32 %a, -4096
116116
ret i32 %1
@@ -127,8 +127,8 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
127127
; RV64I-LABEL: add_negative_low_bound_reject:
128128
; RV64I: # %bb.0:
129129
; RV64I-NEXT: lui a1, 1048575
130-
; RV64I-NEXT: addiw a1, a1, -1
131-
; RV64I-NEXT: add a0, a0, a1
130+
; RV64I-NEXT: addi a1, a1, -1
131+
; RV64I-NEXT: addw a0, a0, a1
132132
; RV64I-NEXT: ret
133133
%1 = add i32 %a, -4097
134134
ret i32 %1
@@ -144,7 +144,7 @@ define i32 @add32_accept(i32 %a) nounwind {
144144
; RV64I-LABEL: add32_accept:
145145
; RV64I: # %bb.0:
146146
; RV64I-NEXT: addi a0, a0, 2047
147-
; RV64I-NEXT: addi a0, a0, 952
147+
; RV64I-NEXT: addiw a0, a0, 952
148148
; RV64I-NEXT: ret
149149
%1 = add i32 %a, 2999
150150
ret i32 %1

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ define i32 @add_i8_signext_i32(i8 %a, i8 %b) {
3737
; RV64IM-NEXT: slli a1, a1, 56
3838
; RV64IM-NEXT: srai a0, a0, 56
3939
; RV64IM-NEXT: srai a1, a1, 56
40-
; RV64IM-NEXT: add a0, a0, a1
40+
; RV64IM-NEXT: addw a0, a0, a1
4141
; RV64IM-NEXT: ret
4242
entry:
4343
%0 = sext i8 %a to i32
@@ -58,7 +58,7 @@ define i32 @add_i8_zeroext_i32(i8 %a, i8 %b) {
5858
; RV64IM: # %bb.0: # %entry
5959
; RV64IM-NEXT: andi a0, a0, 255
6060
; RV64IM-NEXT: andi a1, a1, 255
61-
; RV64IM-NEXT: add a0, a0, a1
61+
; RV64IM-NEXT: addw a0, a0, a1
6262
; RV64IM-NEXT: ret
6363
entry:
6464
%0 = zext i8 %a to i32
@@ -78,7 +78,7 @@ define i32 @add_i32(i32 %a, i32 %b) {
7878
;
7979
; RV64IM-LABEL: add_i32:
8080
; RV64IM: # %bb.0: # %entry
81-
; RV64IM-NEXT: add a0, a0, a1
81+
; RV64IM-NEXT: addw a0, a0, a1
8282
; RV64IM-NEXT: ret
8383
entry:
8484
%0 = add i32 %a, %b
@@ -93,7 +93,7 @@ define i32 @addi_i32(i32 %a) {
9393
;
9494
; RV64IM-LABEL: addi_i32:
9595
; RV64IM: # %bb.0: # %entry
96-
; RV64IM-NEXT: addi a0, a0, 1234
96+
; RV64IM-NEXT: addiw a0, a0, 1234
9797
; RV64IM-NEXT: ret
9898
entry:
9999
%0 = add i32 %a, 1234
@@ -123,7 +123,7 @@ define i32 @subi_i32(i32 %a) {
123123
;
124124
; RV64IM-LABEL: subi_i32:
125125
; RV64IM: # %bb.0: # %entry
126-
; RV64IM-NEXT: addi a0, a0, -1234
126+
; RV64IM-NEXT: addiw a0, a0, -1234
127127
; RV64IM-NEXT: ret
128128
entry:
129129
%0 = sub i32 %a, 1234

‎llvm/test/CodeGen/RISCV/GlobalISel/combine.ll

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ define i32 @constant_to_rhs(i32 %x) {
2121
; RV64-O0-NEXT: mv a1, a0
2222
; RV64-O0-NEXT: li a0, 1
2323
; RV64-O0-NEXT: add a0, a0, a1
24+
; RV64-O0-NEXT: sext.w a0, a0
2425
; RV64-O0-NEXT: ret
2526
;
2627
; RV32-OPT-LABEL: constant_to_rhs:
@@ -30,7 +31,7 @@ define i32 @constant_to_rhs(i32 %x) {
3031
;
3132
; RV64-OPT-LABEL: constant_to_rhs:
3233
; RV64-OPT: # %bb.0:
33-
; RV64-OPT-NEXT: addi a0, a0, 1
34+
; RV64-OPT-NEXT: addiw a0, a0, 1
3435
; RV64-OPT-NEXT: ret
3536
%a = add i32 1, %x
3637
ret i32 %a

‎llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll

Lines changed: 41 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -96,12 +96,19 @@ define ptr @freeze_ptr(ptr %x) {
9696
%struct.T = type { i32, i32 }
9797

9898
define i32 @freeze_struct(ptr %p) {
99-
; CHECK-LABEL: freeze_struct:
100-
; CHECK: # %bb.0:
101-
; CHECK-NEXT: lw a1, 0(a0)
102-
; CHECK-NEXT: lw a0, 4(a0)
103-
; CHECK-NEXT: add a0, a1, a0
104-
; CHECK-NEXT: ret
99+
; RV32-LABEL: freeze_struct:
100+
; RV32: # %bb.0:
101+
; RV32-NEXT: lw a1, 0(a0)
102+
; RV32-NEXT: lw a0, 4(a0)
103+
; RV32-NEXT: add a0, a1, a0
104+
; RV32-NEXT: ret
105+
;
106+
; RV64-LABEL: freeze_struct:
107+
; RV64: # %bb.0:
108+
; RV64-NEXT: lw a1, 0(a0)
109+
; RV64-NEXT: lw a0, 4(a0)
110+
; RV64-NEXT: addw a0, a1, a0
111+
; RV64-NEXT: ret
105112
%s = load %struct.T, ptr %p
106113
%y1 = freeze %struct.T %s
107114
%v1 = extractvalue %struct.T %y1, 0
@@ -111,12 +118,19 @@ define i32 @freeze_struct(ptr %p) {
111118
}
112119

113120
define i32 @freeze_anonstruct(ptr %p) {
114-
; CHECK-LABEL: freeze_anonstruct:
115-
; CHECK: # %bb.0:
116-
; CHECK-NEXT: lw a1, 0(a0)
117-
; CHECK-NEXT: lw a0, 4(a0)
118-
; CHECK-NEXT: add a0, a1, a0
119-
; CHECK-NEXT: ret
121+
; RV32-LABEL: freeze_anonstruct:
122+
; RV32: # %bb.0:
123+
; RV32-NEXT: lw a1, 0(a0)
124+
; RV32-NEXT: lw a0, 4(a0)
125+
; RV32-NEXT: add a0, a1, a0
126+
; RV32-NEXT: ret
127+
;
128+
; RV64-LABEL: freeze_anonstruct:
129+
; RV64: # %bb.0:
130+
; RV64-NEXT: lw a1, 0(a0)
131+
; RV64-NEXT: lw a0, 4(a0)
132+
; RV64-NEXT: addw a0, a1, a0
133+
; RV64-NEXT: ret
120134
%s = load {i32, i32}, ptr %p
121135
%y1 = freeze {i32, i32} %s
122136
%v1 = extractvalue {i32, i32} %y1, 0
@@ -141,7 +155,7 @@ define i32 @freeze_anonstruct2(ptr %p) {
141155
; RV64-NEXT: lw a0, 0(a0)
142156
; RV64-NEXT: slli a1, a1, 48
143157
; RV64-NEXT: srli a1, a1, 48
144-
; RV64-NEXT: add a0, a0, a1
158+
; RV64-NEXT: addw a0, a0, a1
145159
; RV64-NEXT: ret
146160
%s = load {i32, i16}, ptr %p
147161
%y1 = freeze {i32, i16} %s
@@ -168,7 +182,7 @@ define i32 @freeze_anonstruct2_sext(ptr %p) {
168182
; RV64-NEXT: lw a0, 0(a0)
169183
; RV64-NEXT: slli a1, a1, 48
170184
; RV64-NEXT: srai a1, a1, 48
171-
; RV64-NEXT: add a0, a0, a1
185+
; RV64-NEXT: addw a0, a0, a1
172186
; RV64-NEXT: ret
173187
%s = load {i32, i16}, ptr %p
174188
%y1 = freeze {i32, i16} %s
@@ -180,12 +194,19 @@ define i32 @freeze_anonstruct2_sext(ptr %p) {
180194
}
181195

182196
define i32 @freeze_array(ptr %p) nounwind {
183-
; CHECK-LABEL: freeze_array:
184-
; CHECK: # %bb.0:
185-
; CHECK-NEXT: lw a1, 0(a0)
186-
; CHECK-NEXT: lw a0, 4(a0)
187-
; CHECK-NEXT: add a0, a1, a0
188-
; CHECK-NEXT: ret
197+
; RV32-LABEL: freeze_array:
198+
; RV32: # %bb.0:
199+
; RV32-NEXT: lw a1, 0(a0)
200+
; RV32-NEXT: lw a0, 4(a0)
201+
; RV32-NEXT: add a0, a1, a0
202+
; RV32-NEXT: ret
203+
;
204+
; RV64-LABEL: freeze_array:
205+
; RV64: # %bb.0:
206+
; RV64-NEXT: lw a1, 0(a0)
207+
; RV64-NEXT: lw a0, 4(a0)
208+
; RV64-NEXT: addw a0, a1, a0
209+
; RV64-NEXT: ret
189210
%s = load [2 x i32], ptr %p
190211
%y1 = freeze [2 x i32] %s
191212
%v1 = extractvalue [2 x i32] %y1, 0

‎llvm/test/CodeGen/RISCV/GlobalISel/iabs.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ define i32 @abs32(i32 %x) {
9898
; RV64I-LABEL: abs32:
9999
; RV64I: # %bb.0:
100100
; RV64I-NEXT: sraiw a1, a0, 31
101-
; RV64I-NEXT: add a0, a0, a1
101+
; RV64I-NEXT: addw a0, a0, a1
102102
; RV64I-NEXT: xor a0, a0, a1
103103
; RV64I-NEXT: ret
104104
;

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@
2323
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
2424
#
2525
# DEBUG-NEXT: G_SUB (opcode [[SUB_OPC:[0-9]+]]): 1 type index, 0 imm indices
26-
# DEBUG-NEXT: .. opcode [[SUB_OPC]] is aliased to [[ADD_OPC]]
2726
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
2827
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
2928
#

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-rv64.mir

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -86,9 +86,10 @@ body: |
8686
; RV64I-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
8787
; RV64I-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[ASSERT_SEXT]], [[C]](s64)
8888
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[ASSERT_SEXT]], [[ASHR]]
89-
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
90-
; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32
91-
; RV64I-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
89+
; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
90+
; RV64I-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[SEXT_INREG]], [[ASHR]]
91+
; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[XOR]], 32
92+
; RV64I-NEXT: $x10 = COPY [[SEXT_INREG1]](s64)
9293
; RV64I-NEXT: PseudoRET implicit $x10
9394
;
9495
; RV64ZBB-LABEL: name: abs_i32

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-add-rv64.mir

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,8 @@ body: |
6969
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
7070
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
7171
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
72-
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
72+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
73+
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
7374
; CHECK-NEXT: PseudoRET implicit $x10
7475
%0:_(s64) = COPY $x10
7576
%1:_(s64) = COPY $x11

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-addo-subo-rv64.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -339,7 +339,7 @@ body: |
339339
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
340340
; CHECK-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY1]], 32
341341
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s64) = G_ICMP intpred(ult), [[SEXT_INREG]](s64), [[SEXT_INREG1]]
342-
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
342+
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
343343
; CHECK-NEXT: $x11 = COPY [[ICMP]](s64)
344344
; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
345345
%2:_(s64) = COPY $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-const-rv64.mir

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,8 @@ body: |
145145
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -64769
146146
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
147147
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]]
148-
; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
148+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
149+
; CHECK-NEXT: $x10 = COPY [[SEXT_INREG]](s64)
149150
; CHECK-NEXT: PseudoRET implicit $x10
150151
%0:_(s32) = G_CONSTANT i32 -64769
151152
%1:_(s64) = COPY $x10

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir

Lines changed: 10 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -181,10 +181,12 @@ body: |
181181
; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]]
182182
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]]
183183
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]]
184-
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64)
185-
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]]
184+
; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
185+
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG]], [[C3]](s64)
186+
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG]]
187+
; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32
186188
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135
187-
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]]
189+
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C8]]
188190
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009
189191
; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
190192
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]]
@@ -450,10 +452,12 @@ body: |
450452
; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[LSHR6]], [[C7]]
451453
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[SUB]], [[C7]]
452454
; RV64I-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[AND8]], [[AND9]]
453-
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[ADD]], [[C3]](s64)
454-
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[ADD]]
455+
; RV64I-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD]], 32
456+
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s64) = G_LSHR [[SEXT_INREG]], [[C3]](s64)
457+
; RV64I-NEXT: [[ADD1:%[0-9]+]]:_(s64) = G_ADD [[LSHR7]], [[SEXT_INREG]]
458+
; RV64I-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s64) = G_SEXT_INREG [[ADD1]], 32
455459
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s64) = G_CONSTANT i64 252645135
456-
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[ADD1]], [[C8]]
460+
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s64) = G_AND [[SEXT_INREG1]], [[C8]]
457461
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s64) = G_CONSTANT i64 16843009
458462
; RV64I-NEXT: [[C10:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
459463
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[AND10]], [[C9]]

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