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Minor refactorings / comment updates
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bolt/lib/Passes/PAuthGadgetScanner.cpp

Lines changed: 19 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -152,6 +152,8 @@ class TrackedRegisters {
152152
// in the gadgets to be reported. This information is used in the second run
153153
// to also track which instructions last wrote to those registers.
154154

155+
typedef SmallPtrSet<const MCInst *, 4> SetOfRelatedInsts;
156+
155157
/// A state representing which registers are safe to use by an instruction
156158
/// at a given program point.
157159
///
@@ -195,7 +197,7 @@ struct SrcState {
195197
/// pac-ret analysis, the expectation is that almost all return instructions
196198
/// only use register `X30`, and therefore, this vector will probably have
197199
/// length 1 in the second run.
198-
std::vector<SmallPtrSet<const MCInst *, 4>> LastInstWritingReg;
200+
std::vector<SetOfRelatedInsts> LastInstWritingReg;
199201

200202
/// Construct an empty state.
201203
SrcState() {}
@@ -231,7 +233,7 @@ struct SrcState {
231233
};
232234

233235
static void printInstsShort(raw_ostream &OS,
234-
ArrayRef<SmallPtrSet<const MCInst *, 4>> Insts) {
236+
ArrayRef<SetOfRelatedInsts> Insts) {
235237
OS << "Insts: ";
236238
for (unsigned I = 0; I < Insts.size(); ++I) {
237239
auto &Set = Insts[I];
@@ -322,13 +324,12 @@ class SrcSafetyAnalysis {
322324
DenseMap<const MCInst *, std::pair<MCPhysReg, const MCInst *>>
323325
CheckerSequenceInfo;
324326

325-
SmallPtrSet<const MCInst *, 4> &lastWritingInsts(SrcState &S,
326-
MCPhysReg Reg) const {
327+
SetOfRelatedInsts &lastWritingInsts(SrcState &S, MCPhysReg Reg) const {
327328
unsigned Index = RegsToTrackInstsFor.getIndex(Reg);
328329
return S.LastInstWritingReg[Index];
329330
}
330-
const SmallPtrSet<const MCInst *, 4> &lastWritingInsts(const SrcState &S,
331-
MCPhysReg Reg) const {
331+
const SetOfRelatedInsts &lastWritingInsts(const SrcState &S,
332+
MCPhysReg Reg) const {
332333
unsigned Index = RegsToTrackInstsFor.getIndex(Reg);
333334
return S.LastInstWritingReg[Index];
334335
}
@@ -742,8 +743,8 @@ SrcSafetyAnalysis::create(BinaryFunction &BF,
742743
/// A state representing which registers are safe to be used as the destination
743744
/// operand of an authentication instruction.
744745
///
745-
/// Similar to SrcState, it is the analysis that should take register aliasing
746-
/// into account.
746+
/// Similar to SrcState, it is the responsibility of the analysis to take
747+
/// register aliasing into account.
747748
///
748749
/// Depending on the implementation, it may be possible that an authentication
749750
/// instruction returns an invalid pointer on failure instead of terminating
@@ -777,9 +778,9 @@ struct DstState {
777778
/// instructions should only be written to such registers.
778779
BitVector CannotEscapeUnchecked;
779780

780-
std::vector<SmallPtrSet<const MCInst *, 4>> FirstInstLeakingReg;
781+
std::vector<SetOfRelatedInsts> FirstInstLeakingReg;
781782

782-
/// Construct an empty state.
783+
/// Constructs an empty state.
783784
DstState() {}
784785

785786
DstState(unsigned NumRegs, unsigned NumRegsToTrack)
@@ -882,13 +883,12 @@ class DstSafetyAnalysis {
882883
/// operates on separate instructions.
883884
DenseMap<const MCInst *, MCPhysReg> RegCheckedAt;
884885

885-
SmallPtrSet<const MCInst *, 4> &firstLeakingInsts(DstState &S,
886-
MCPhysReg Reg) const {
886+
SetOfRelatedInsts &firstLeakingInsts(DstState &S, MCPhysReg Reg) const {
887887
unsigned Index = RegsToTrackInstsFor.getIndex(Reg);
888888
return S.FirstInstLeakingReg[Index];
889889
}
890-
const SmallPtrSet<const MCInst *, 4> &firstLeakingInsts(const DstState &S,
891-
MCPhysReg Reg) const {
890+
const SetOfRelatedInsts &firstLeakingInsts(const DstState &S,
891+
MCPhysReg Reg) const {
892892
unsigned Index = RegsToTrackInstsFor.getIndex(Reg);
893893
return S.FirstInstLeakingReg[Index];
894894
}
@@ -899,6 +899,9 @@ class DstSafetyAnalysis {
899899
return DstState(NumRegs, RegsToTrackInstsFor.getNumTrackedRegisters());
900900
}
901901

902+
/// Returns the set of registers that can be leaked by this instruction.
903+
/// This is computed similar to the set of clobbered registers, but taking
904+
/// input operands instead of outputs.
902905
BitVector getLeakedRegs(const MCInst &Inst) const {
903906
BitVector Leaked(NumRegs);
904907

@@ -1067,6 +1070,8 @@ class DataflowDstSafetyAnalysis
10671070
: DstSafetyAnalysis(BF, RegsToTrackInstsFor), DFParent(BF, AllocId) {}
10681071

10691072
const DstState &getStateAfter(const MCInst &Inst) const override {
1073+
// The dataflow analysis base class iterates backwards over the
1074+
// instructions, thus "after" vs. "before" difference.
10701075
return DFParent::getStateBefore(Inst).get();
10711076
}
10721077

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