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author
Johnny Chen
committed
A8.6.393
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ llvm-svn: 129033
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‎llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Lines changed: 47 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -2497,22 +2497,22 @@ static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
24972497
// 0 represents standard alignment, i.e., unaligned data access.
24982498
unsigned alignment = 0;
24992499

2500-
if (Name.find("LN") != std::string::npos) {
2501-
// To one lane instructions.
2502-
// See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
2500+
unsigned elem = 0; // legal values: {1, 2, 3, 4}
2501+
if (Name.startswith("VST1") || Name.startswith("VLD1"))
2502+
elem = 1;
25032503

2504-
unsigned elem = 0; // legal values: {1, 2, 3, 4}
2505-
if (Name.startswith("VST1") || Name.startswith("VLD1"))
2506-
elem = 1;
2504+
if (Name.startswith("VST2") || Name.startswith("VLD2"))
2505+
elem = 2;
25072506

2508-
if (Name.startswith("VST2") || Name.startswith("VLD2"))
2509-
elem = 2;
2507+
if (Name.startswith("VST3") || Name.startswith("VLD3"))
2508+
elem = 3;
25102509

2511-
if (Name.startswith("VST3") || Name.startswith("VLD3"))
2512-
elem = 3;
2510+
if (Name.startswith("VST4") || Name.startswith("VLD4"))
2511+
elem = 4;
25132512

2514-
if (Name.startswith("VST4") || Name.startswith("VLD4"))
2515-
elem = 4;
2513+
if (Name.find("LN") != std::string::npos) {
2514+
// To one lane instructions.
2515+
// See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
25162516

25172517
// Utility function takes number of elements, size, and index_align.
25182518
if (!Align4OneLaneInst(elem,
@@ -2533,7 +2533,8 @@ static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
25332533
// See, for example, A8.6.316 VLD4 (multiple 4-element structures).
25342534

25352535
// Inst{5-4} encodes alignment.
2536-
switch (slice(insn, 5, 4)) {
2536+
unsigned align = slice(insn, 5, 4);
2537+
switch (align) {
25372538
default:
25382539
break;
25392540
case 1:
@@ -2544,22 +2545,42 @@ static bool DisassembleNLdSt(MCInst &MI, unsigned Opcode, uint32_t insn,
25442545
alignment = 256; break;
25452546
}
25462547

2547-
// n == 2 && type == 0b1001 -> DblSpaced = true
2548-
if (Name.startswith("VST2") || Name.startswith("VLD2"))
2549-
DblSpaced = slice(insn, 11, 8) == 9;
2550-
2551-
// n == 3 && type == 0b0101 -> DblSpaced = true
2552-
if (Name.startswith("VST3") || Name.startswith("VLD3")) {
2548+
unsigned type = slice(insn, 11, 8);
2549+
// Reject UNDEFINED instructions based on type and align.
2550+
// Plus set DblSpaced flag where appropriate.
2551+
switch (elem) {
2552+
default:
2553+
break;
2554+
case 1:
2555+
// n == 1
2556+
// A8.6.307 & A8.6.391
2557+
if ((type == 7 && slice(align, 1, 1) == 1) ||
2558+
(type == 10 && align == 3) ||
2559+
(type == 6 && slice(align, 1, 1) == 1))
2560+
return false;
2561+
break;
2562+
case 2:
2563+
// n == 2 && type == 0b1001 -> DblSpaced = true
2564+
// A8.6.310 & A8.6.393
2565+
if ((type == 8 || type == 9) && align == 3)
2566+
return false;
2567+
DblSpaced = (type == 9);
2568+
break;
2569+
case 3:
2570+
// n == 3 && type == 0b0101 -> DblSpaced = true
25532571
// A8.6.313 & A8.6.395
2554-
if (slice(insn, 7, 6) == 3 && slice(insn, 5, 5) == 1)
2572+
if (slice(insn, 7, 6) == 3 || slice(align, 1, 1) == 1)
25552573
return false;
2556-
2557-
DblSpaced = slice(insn, 11, 8) == 5;
2574+
DblSpaced = (type == 5);
2575+
break;
2576+
case 4:
2577+
// n == 4 && type == 0b0001 -> DblSpaced = true
2578+
// A8.6.316 & A8.6.397
2579+
if (slice(insn, 7, 6) == 3)
2580+
return false;
2581+
DblSpaced = (type == 1);
2582+
break;
25582583
}
2559-
2560-
// n == 4 && type == 0b0001 -> DblSpaced = true
2561-
if (Name.startswith("VST4") || Name.startswith("VLD4"))
2562-
DblSpaced = slice(insn, 11, 8) == 1;
25632584
}
25642585
return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
25652586
slice(insn, 21, 21) == 0, DblSpaced, alignment/8, B);

‎llvm/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
2+
3+
# Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
4+
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
5+
# -------------------------------------------------------------------------------------------------
6+
# | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
7+
# -------------------------------------------------------------------------------------------------
8+
#
9+
# A8.6.393 VST2 (multiple 2-element structures)
10+
# type == '1001' and align == '11' ==> UNDEFINED
11+
0xb3 0x9 0x3 0xf4

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