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Convert as many LivePhysRegs uses to LiveRegUnits
1 parent e96c0c1 commit bdce349

10 files changed

+84
-93
lines changed

‎llvm/lib/CodeGen/ReachingDefAnalysis.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,10 @@
66
//
77
//===----------------------------------------------------------------------===//
88

9-
#include "llvm/ADT/SmallSet.h"
10-
#include "llvm/ADT/SetOperations.h"
11-
#include "llvm/CodeGen/LivePhysRegs.h"
129
#include "llvm/CodeGen/ReachingDefAnalysis.h"
10+
#include "llvm/ADT/SetOperations.h"
11+
#include "llvm/ADT/SmallSet.h"
12+
#include "llvm/CodeGen/LiveRegUnits.h"
1313
#include "llvm/CodeGen/TargetRegisterInfo.h"
1414
#include "llvm/CodeGen/TargetSubtargetInfo.h"
1515
#include "llvm/Support/Debug.h"
@@ -421,9 +421,9 @@ void ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB,
421421
return;
422422

423423
VisitedBBs.insert(MBB);
424-
LivePhysRegs LiveRegs(*TRI);
424+
LiveRegUnits LiveRegs(*TRI);
425425
LiveRegs.addLiveOuts(*MBB);
426-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
426+
if (LiveRegs.available(PhysReg))
427427
return;
428428

429429
if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg))
@@ -469,19 +469,19 @@ MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI,
469469
bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI,
470470
MCRegister PhysReg) const {
471471
MachineBasicBlock *MBB = MI->getParent();
472-
LivePhysRegs LiveRegs(*TRI);
472+
LiveRegUnits LiveRegs(*TRI);
473473
LiveRegs.addLiveOuts(*MBB);
474474

475475
// Yes if the register is live out of the basic block.
476-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
476+
if (!LiveRegs.available(PhysReg))
477477
return true;
478478

479479
// Walk backwards through the block to see if the register is live at some
480480
// point.
481481
for (MachineInstr &Last :
482482
instructionsWithoutDebug(MBB->instr_rbegin(), MBB->instr_rend())) {
483483
LiveRegs.stepBackward(Last);
484-
if (!LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
484+
if (!LiveRegs.available(PhysReg))
485485
return InstIds.lookup(&Last) > InstIds.lookup(MI);
486486
}
487487
return false;
@@ -504,9 +504,9 @@ bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI,
504504
bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
505505
MCRegister PhysReg) const {
506506
MachineBasicBlock *MBB = MI->getParent();
507-
LivePhysRegs LiveRegs(*TRI);
507+
LiveRegUnits LiveRegs(*TRI);
508508
LiveRegs.addLiveOuts(*MBB);
509-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
509+
if (LiveRegs.available(PhysReg))
510510
return false;
511511

512512
auto Last = MBB->getLastNonDebugInstr();
@@ -525,9 +525,9 @@ bool ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI,
525525
MachineInstr *
526526
ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB,
527527
MCRegister PhysReg) const {
528-
LivePhysRegs LiveRegs(*TRI);
528+
LiveRegUnits LiveRegs(*TRI);
529529
LiveRegs.addLiveOuts(*MBB);
530-
if (LiveRegs.available(MBB->getParent()->getRegInfo(), PhysReg))
530+
if (LiveRegs.available(PhysReg))
531531
return nullptr;
532532

533533
auto Last = MBB->getLastNonDebugInstr();

‎llvm/lib/CodeGen/StackMapLivenessAnalysis.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
//===----------------------------------------------------------------------===//
1414

1515
#include "llvm/ADT/Statistic.h"
16-
#include "llvm/CodeGen/LivePhysRegs.h"
16+
#include "llvm/CodeGen/LiveRegUnits.h"
1717
#include "llvm/CodeGen/MachineFrameInfo.h"
1818
#include "llvm/CodeGen/MachineFunction.h"
1919
#include "llvm/CodeGen/MachineFunctionPass.h"
@@ -49,7 +49,7 @@ namespace {
4949
/// aformentioned intrinsic to function.
5050
class StackMapLiveness : public MachineFunctionPass {
5151
const TargetRegisterInfo *TRI = nullptr;
52-
LivePhysRegs LiveRegs;
52+
LiveRegUnits LiveRegs;
5353

5454
public:
5555
static char ID;
@@ -126,8 +126,7 @@ bool StackMapLiveness::calculateLiveness(MachineFunction &MF) {
126126
for (auto &MBB : MF) {
127127
LLVM_DEBUG(dbgs() << "****** BB " << MBB.getName() << " ******\n");
128128
LiveRegs.init(*TRI);
129-
// FIXME: This should probably be addLiveOuts().
130-
LiveRegs.addLiveOutsNoPristines(MBB);
129+
LiveRegs.addLiveOuts(MBB);
131130
bool HasStackMap = false;
132131
// Reverse iterate over all instructions and add the current live register
133132
// set to an instruction if we encounter a patchpoint instruction.
@@ -161,7 +160,7 @@ void StackMapLiveness::addLiveOutSetToMI(MachineFunction &MF,
161160
uint32_t *StackMapLiveness::createRegisterMask(MachineFunction &MF) const {
162161
// The mask is owned and cleaned up by the Machine Function.
163162
uint32_t *Mask = MF.allocateRegMask();
164-
for (auto Reg : LiveRegs)
163+
for (auto Reg : LiveRegs.getBitVector().set_bits())
165164
Mask[Reg / 32] |= 1U << (Reg % 32);
166165

167166
// Give the target a chance to adjust the mask.

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -197,6 +197,7 @@
197197
#include "llvm/ADT/SmallVector.h"
198198
#include "llvm/ADT/Statistic.h"
199199
#include "llvm/CodeGen/LivePhysRegs.h"
200+
#include "llvm/CodeGen/LiveRegUnits.h"
200201
#include "llvm/CodeGen/MachineBasicBlock.h"
201202
#include "llvm/CodeGen/MachineFrameInfo.h"
202203
#include "llvm/CodeGen/MachineFunction.h"
@@ -988,7 +989,7 @@ void AArch64FrameLowering::emitZeroCallUsedRegs(BitVector RegsToZero,
988989
}
989990
}
990991

991-
static void getLiveRegsForEntryMBB(LivePhysRegs &LiveRegs,
992+
static void getLiveRegsForEntryMBB(LiveRegUnits &LiveRegs,
992993
const MachineBasicBlock &MBB) {
993994
const MachineFunction *MF = MBB.getParent();
994995
LiveRegs.addLiveIns(MBB);
@@ -1018,16 +1019,15 @@ static Register findScratchNonCalleeSaveRegister(MachineBasicBlock *MBB) {
10181019

10191020
const AArch64Subtarget &Subtarget = MF->getSubtarget<AArch64Subtarget>();
10201021
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
1021-
LivePhysRegs LiveRegs(TRI);
1022+
LiveRegUnits LiveRegs(TRI);
10221023
getLiveRegsForEntryMBB(LiveRegs, *MBB);
10231024

10241025
// Prefer X9 since it was historically used for the prologue scratch reg.
1025-
const MachineRegisterInfo &MRI = MF->getRegInfo();
1026-
if (LiveRegs.available(MRI, AArch64::X9))
1026+
if (LiveRegs.available(AArch64::X9))
10271027
return AArch64::X9;
10281028

1029-
for (unsigned Reg : AArch64::GPR64RegClass) {
1030-
if (LiveRegs.available(MRI, Reg))
1029+
for (Register Reg : AArch64::GPR64RegClass) {
1030+
if (LiveRegs.available(Reg))
10311031
return Reg;
10321032
}
10331033
return AArch64::NoRegister;
@@ -1044,13 +1044,11 @@ bool AArch64FrameLowering::canUseAsPrologue(
10441044

10451045
if (AFI->hasSwiftAsyncContext()) {
10461046
const AArch64RegisterInfo &TRI = *Subtarget.getRegisterInfo();
1047-
const MachineRegisterInfo &MRI = MF->getRegInfo();
1048-
LivePhysRegs LiveRegs(TRI);
1047+
LiveRegUnits LiveRegs(TRI);
10491048
getLiveRegsForEntryMBB(LiveRegs, MBB);
10501049
// The StoreSwiftAsyncContext clobbers X16 and X17. Make sure they are
10511050
// available.
1052-
if (!LiveRegs.available(MRI, AArch64::X16) ||
1053-
!LiveRegs.available(MRI, AArch64::X17))
1051+
if (!LiveRegs.available(AArch64::X16) || !LiveRegs.available(AArch64::X17))
10541052
return false;
10551053
}
10561054

‎llvm/lib/Target/AMDGPU/SIOptimizeExecMasking.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
1212
#include "SIRegisterInfo.h"
1313
#include "llvm/ADT/SmallVector.h"
14-
#include "llvm/CodeGen/LivePhysRegs.h"
14+
#include "llvm/CodeGen/LiveRegUnits.h"
1515
#include "llvm/CodeGen/MachineFunctionPass.h"
1616
#include "llvm/CodeGen/MachineOperand.h"
1717
#include "llvm/CodeGen/TargetRegisterInfo.h"
@@ -313,7 +313,7 @@ MachineBasicBlock::reverse_iterator SIOptimizeExecMasking::findExecCopy(
313313
return E;
314314
}
315315

316-
// XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
316+
// XXX - Seems LiveRegUnits doesn't work correctly since it will incorrectly
317317
// report the register as unavailable because a super-register with a lane mask
318318
// is unavailable.
319319
static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
@@ -383,7 +383,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
383383
MCRegister Reg,
384384
bool UseLiveOuts,
385385
bool IgnoreStart) const {
386-
LivePhysRegs LR(*TRI);
386+
LiveRegUnits LR(*TRI);
387387
if (UseLiveOuts)
388388
LR.addLiveOuts(*Stop.getParent());
389389

@@ -396,7 +396,7 @@ bool SIOptimizeExecMasking::isRegisterInUseBetween(MachineInstr &Stop,
396396
LR.stepBackward(*A);
397397
}
398398

399-
return !LR.available(*MRI, Reg);
399+
return !LR.available(Reg);
400400
}
401401

402402
// Determine if a register Reg is not re-defined and still in use

‎llvm/lib/Target/ARM/ARMConstantIslandPass.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@
2727
#include "llvm/ADT/SmallVector.h"
2828
#include "llvm/ADT/Statistic.h"
2929
#include "llvm/ADT/StringRef.h"
30-
#include "llvm/CodeGen/LivePhysRegs.h"
30+
#include "llvm/CodeGen/LiveRegUnits.h"
3131
#include "llvm/CodeGen/MachineBasicBlock.h"
3232
#include "llvm/CodeGen/MachineConstantPool.h"
3333
#include "llvm/CodeGen/MachineDominators.h"
@@ -990,7 +990,7 @@ MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
990990
MachineBasicBlock *OrigBB = MI->getParent();
991991

992992
// Collect liveness information at MI.
993-
LivePhysRegs LRs(*MF->getSubtarget().getRegisterInfo());
993+
LiveRegUnits LRs(*MF->getSubtarget().getRegisterInfo());
994994
LRs.addLiveOuts(*OrigBB);
995995
auto LivenessEnd = ++MachineBasicBlock::iterator(MI).getReverse();
996996
for (MachineInstr &LiveMI : make_range(OrigBB->rbegin(), LivenessEnd))
@@ -1026,7 +1026,7 @@ MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
10261026

10271027
// Update live-in information in the new block.
10281028
MachineRegisterInfo &MRI = MF->getRegInfo();
1029-
for (MCPhysReg L : LRs)
1029+
for (MCPhysReg L : LRs.getBitVector().set_bits())
10301030
if (!MRI.isReserved(L))
10311031
NewBB->addLiveIn(L);
10321032

‎llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@
3131
#include "llvm/ADT/Statistic.h"
3232
#include "llvm/ADT/iterator_range.h"
3333
#include "llvm/Analysis/AliasAnalysis.h"
34-
#include "llvm/CodeGen/LivePhysRegs.h"
34+
#include "llvm/CodeGen/LiveRegUnits.h"
3535
#include "llvm/CodeGen/MachineBasicBlock.h"
3636
#include "llvm/CodeGen/MachineDominators.h"
3737
#include "llvm/CodeGen/MachineFrameInfo.h"
@@ -109,7 +109,7 @@ namespace {
109109
const ARMSubtarget *STI;
110110
const TargetLowering *TL;
111111
ARMFunctionInfo *AFI;
112-
LivePhysRegs LiveRegs;
112+
LiveRegUnits LiveRegs;
113113
RegisterClassInfo RegClassInfo;
114114
MachineBasicBlock::const_iterator LiveRegPos;
115115
bool LiveRegsValid;
@@ -589,7 +589,7 @@ unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
589589
}
590590

591591
for (unsigned Reg : RegClassInfo.getOrder(&RegClass))
592-
if (LiveRegs.available(MF->getRegInfo(), Reg))
592+
if (LiveRegs.available(Reg))
593593
return Reg;
594594
return 0;
595595
}

‎llvm/lib/Target/ARM/Thumb1FrameLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -612,11 +612,11 @@ bool Thumb1FrameLowering::needPopSpecialFixUp(const MachineFunction &MF) const {
612612

613613
static void findTemporariesForLR(const BitVector &GPRsNoLRSP,
614614
const BitVector &PopFriendly,
615-
const LivePhysRegs &UsedRegs, unsigned &PopReg,
615+
const LiveRegUnits &UsedRegs, unsigned &PopReg,
616616
unsigned &TmpReg, MachineRegisterInfo &MRI) {
617617
PopReg = TmpReg = 0;
618618
for (auto Reg : GPRsNoLRSP.set_bits()) {
619-
if (UsedRegs.available(MRI, Reg)) {
619+
if (UsedRegs.available(Reg)) {
620620
// Remember the first pop-friendly register and exit.
621621
if (PopFriendly.test(Reg)) {
622622
PopReg = Reg;
@@ -684,7 +684,7 @@ bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
684684
// Look for a temporary register to use.
685685
// First, compute the liveness information.
686686
const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
687-
LivePhysRegs UsedRegs(TRI);
687+
LiveRegUnits UsedRegs(TRI);
688688
UsedRegs.addLiveOuts(MBB);
689689
// The semantic of pristines changed recently and now,
690690
// the callee-saved registers that are touched in the function

‎llvm/test/CodeGen/AArch64/arm64-shrink-wrapping.ll

Lines changed: 22 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1028,23 +1028,31 @@ false:
10281028
ret i32 %tmp.0
10291029
}
10301030

1031-
; Re-aligned stack pointer with all caller-save regs live. See bug
1032-
; 26642. In this case we currently avoid shrink wrapping because
1033-
; ensuring we have a scratch register to re-align the stack pointer is
1034-
; too complicated. Output should be the same for both enabled and
1035-
; disabled shrink wrapping.
1031+
; Re-aligned stack pointer with all caller-save regs live.
10361032
define void @stack_realign2(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %ptr4, ptr %ptr5, ptr %ptr6) {
10371033
; ENABLE-LABEL: stack_realign2:
10381034
; ENABLE: ; %bb.0:
1035+
; ENABLE-NEXT: lsl w8, w1, w0
1036+
; ENABLE-NEXT: lsr w9, w0, w1
1037+
; ENABLE-NEXT: lsl w14, w0, w1
1038+
; ENABLE-NEXT: lsr w11, w1, w0
1039+
; ENABLE-NEXT: add w15, w1, w0
1040+
; ENABLE-NEXT: sub w10, w8, w9
1041+
; ENABLE-NEXT: subs w17, w1, w0
1042+
; ENABLE-NEXT: add w16, w14, w8
1043+
; ENABLE-NEXT: add w12, w9, w11
1044+
; ENABLE-NEXT: add w13, w11, w15
1045+
; ENABLE-NEXT: b.le LBB14_2
1046+
; ENABLE-NEXT: ; %bb.1: ; %true
10391047
; ENABLE-NEXT: stp x28, x27, [sp, #-96]! ; 16-byte Folded Spill
10401048
; ENABLE-NEXT: stp x26, x25, [sp, #16] ; 16-byte Folded Spill
10411049
; ENABLE-NEXT: stp x24, x23, [sp, #32] ; 16-byte Folded Spill
10421050
; ENABLE-NEXT: stp x22, x21, [sp, #48] ; 16-byte Folded Spill
10431051
; ENABLE-NEXT: stp x20, x19, [sp, #64] ; 16-byte Folded Spill
10441052
; ENABLE-NEXT: stp x29, x30, [sp, #80] ; 16-byte Folded Spill
10451053
; ENABLE-NEXT: add x29, sp, #80
1046-
; ENABLE-NEXT: sub x9, sp, #32
1047-
; ENABLE-NEXT: and sp, x9, #0xffffffffffffffe0
1054+
; ENABLE-NEXT: sub x18, sp, #32
1055+
; ENABLE-NEXT: and sp, x18, #0xffffffffffffffe0
10481056
; ENABLE-NEXT: .cfi_def_cfa w29, 16
10491057
; ENABLE-NEXT: .cfi_offset w30, -8
10501058
; ENABLE-NEXT: .cfi_offset w29, -16
@@ -1058,22 +1066,17 @@ define void @stack_realign2(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr
10581066
; ENABLE-NEXT: .cfi_offset w26, -80
10591067
; ENABLE-NEXT: .cfi_offset w27, -88
10601068
; ENABLE-NEXT: .cfi_offset w28, -96
1061-
; ENABLE-NEXT: lsl w8, w1, w0
1062-
; ENABLE-NEXT: lsr w9, w0, w1
1063-
; ENABLE-NEXT: lsl w14, w0, w1
1064-
; ENABLE-NEXT: lsr w11, w1, w0
1065-
; ENABLE-NEXT: add w15, w1, w0
1066-
; ENABLE-NEXT: sub w10, w8, w9
1067-
; ENABLE-NEXT: subs w17, w1, w0
1068-
; ENABLE-NEXT: add w16, w14, w8
1069-
; ENABLE-NEXT: add w12, w9, w11
1070-
; ENABLE-NEXT: add w13, w11, w15
1071-
; ENABLE-NEXT: b.le LBB14_2
1072-
; ENABLE-NEXT: ; %bb.1: ; %true
10731069
; ENABLE-NEXT: str w0, [sp]
10741070
; ENABLE-NEXT: ; InlineAsm Start
10751071
; ENABLE-NEXT: nop
10761072
; ENABLE-NEXT: ; InlineAsm End
1073+
; ENABLE-NEXT: sub sp, x29, #80
1074+
; ENABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
1075+
; ENABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
1076+
; ENABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
1077+
; ENABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
1078+
; ENABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
1079+
; ENABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload
10771080
; ENABLE-NEXT: LBB14_2: ; %false
10781081
; ENABLE-NEXT: str w14, [x2]
10791082
; ENABLE-NEXT: str w8, [x3]
@@ -1084,13 +1087,6 @@ define void @stack_realign2(i32 %a, i32 %b, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr
10841087
; ENABLE-NEXT: stp w0, w1, [x2, #4]
10851088
; ENABLE-NEXT: stp w16, w10, [x2, #12]
10861089
; ENABLE-NEXT: stp w12, w13, [x2, #20]
1087-
; ENABLE-NEXT: sub sp, x29, #80
1088-
; ENABLE-NEXT: ldp x29, x30, [sp, #80] ; 16-byte Folded Reload
1089-
; ENABLE-NEXT: ldp x20, x19, [sp, #64] ; 16-byte Folded Reload
1090-
; ENABLE-NEXT: ldp x22, x21, [sp, #48] ; 16-byte Folded Reload
1091-
; ENABLE-NEXT: ldp x24, x23, [sp, #32] ; 16-byte Folded Reload
1092-
; ENABLE-NEXT: ldp x26, x25, [sp, #16] ; 16-byte Folded Reload
1093-
; ENABLE-NEXT: ldp x28, x27, [sp], #96 ; 16-byte Folded Reload
10941090
; ENABLE-NEXT: ret
10951091
;
10961092
; DISABLE-LABEL: stack_realign2:

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