[CodeGen] Use Register or MCRegister. NFC

Author: topperc

llvm/include/llvm/CodeGen/DetectDeadLanes.h

@@ -37,6 +37,7 @@ namespace llvm {
 class MachineInstr;
 class MachineOperand;
 class MachineRegisterInfo;
+class Register;
 class TargetRegisterInfo;
 
 class DeadLaneDetector {
@@ -92,8 +93,8 @@ class DeadLaneDetector {
                                 const MachineOperand &MO) const;
 
 private:
-  LaneBitmask determineInitialDefinedLanes(unsigned Reg);
-  LaneBitmask determineInitialUsedLanes(unsigned Reg);
+  LaneBitmask determineInitialDefinedLanes(Register Reg);
+  LaneBitmask determineInitialUsedLanes(Register Reg);
 
   const MachineRegisterInfo *MRI;
   const TargetRegisterInfo *TRI;

llvm/include/llvm/CodeGen/ExecutionDomainFix.h

@@ -156,7 +156,7 @@ class ExecutionDomainFix : public MachineFunctionPass {
   /// Translate TRI register number to a list of indices into our smaller tables
   /// of interesting registers.
   iterator_range<SmallVectorImpl<int>::const_iterator>
-  regIndices(unsigned Reg) const;
+  regIndices(MCRegister Reg) const;
 
   /// DomainValue allocation.
   DomainValue *alloc(int domain = -1);

llvm/include/llvm/CodeGen/LiveRangeCalc.h

@@ -147,7 +147,7 @@ class LiveRangeCalc {
   ///
   /// PhysReg, when set, is used to verify live-in lists on basic blocks.
   bool findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB, SlotIndex Use,
-                        unsigned PhysReg, ArrayRef<SlotIndex> Undefs);
+                        Register PhysReg, ArrayRef<SlotIndex> Undefs);
 
   /// updateSSA - Compute the values that will be live in to all requested
   /// blocks in LiveIn.  Create PHI-def values as required to preserve SSA form.
@@ -204,7 +204,7 @@ class LiveRangeCalc {
   /// inserted as required to preserve SSA form.
   ///
   /// PhysReg, when set, is used to verify live-in lists on basic blocks.
-  void extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
+  void extend(LiveRange &LR, SlotIndex Use, Register PhysReg,
               ArrayRef<SlotIndex> Undefs);
 
   //===--------------------------------------------------------------------===//

llvm/include/llvm/CodeGen/LiveRegMatrix.h

@@ -56,7 +56,7 @@ class LiveRegMatrix {
 
   // Cached register mask interference info.
   unsigned RegMaskTag = 0;
-  unsigned RegMaskVirtReg = 0;
+  Register RegMaskVirtReg;
   BitVector RegMaskUsable;
 
   LiveRegMatrix()

llvm/include/llvm/CodeGen/LiveVariables.h

@@ -135,7 +135,7 @@ class LiveVariables {
   // register references are presumed dead across basic blocks.
   std::vector<MachineInstr *> PhysRegUse;
 
-  std::vector<SmallVector<unsigned, 4>> PHIVarInfo;
+  std::vector<SmallVector<Register, 4>> PHIVarInfo;
 
   // DistanceMap - Keep track the distance of a MI from the start of the
   // current basic block.

llvm/lib/CodeGen/AllocationOrder.cpp

@@ -26,7 +26,7 @@ using namespace llvm;
 #define DEBUG_TYPE "regalloc"
 
 // Compare VirtRegMap::getRegAllocPref().
-AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM,
+AllocationOrder AllocationOrder::create(Register VirtReg, const VirtRegMap &VRM,
                                         const RegisterClassInfo &RegClassInfo,
                                         const LiveRegMatrix *Matrix) {
   const MachineFunction &MF = VRM.getMachineFunction();

llvm/lib/CodeGen/AllocationOrder.h

@@ -81,7 +81,7 @@ class LLVM_LIBRARY_VISIBILITY AllocationOrder {
   /// @param VirtReg      Virtual register to allocate for.
   /// @param VRM          Virtual register map for function.
   /// @param RegClassInfo Information about reserved and allocatable registers.
-  static AllocationOrder create(unsigned VirtReg, const VirtRegMap &VRM,
+  static AllocationOrder create(Register VirtReg, const VirtRegMap &VRM,
                                 const RegisterClassInfo &RegClassInfo,
                                 const LiveRegMatrix *Matrix);
 

llvm/lib/CodeGen/DetectDeadLanes.cpp

@@ -265,7 +265,7 @@ LaneBitmask DeadLaneDetector::transferDefinedLanes(
   return DefinedLanes;
 }
 
-LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(unsigned Reg) {
+LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(Register Reg) {
   // Live-In or unused registers have no definition but are considered fully
   // defined.
   if (!MRI->hasOneDef(Reg))
@@ -330,7 +330,7 @@ LaneBitmask DeadLaneDetector::determineInitialDefinedLanes(unsigned Reg) {
   return MRI->getMaxLaneMaskForVReg(Reg);
 }
 
-LaneBitmask DeadLaneDetector::determineInitialUsedLanes(unsigned Reg) {
+LaneBitmask DeadLaneDetector::determineInitialUsedLanes(Register Reg) {
   LaneBitmask UsedLanes = LaneBitmask::getNone();
   for (const MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
     if (!MO.readsReg())

llvm/lib/CodeGen/ExecutionDomainFix.cpp

@@ -16,7 +16,7 @@ using namespace llvm;
 #define DEBUG_TYPE "execution-deps-fix"
 
 iterator_range<SmallVectorImpl<int>::const_iterator>
-ExecutionDomainFix::regIndices(unsigned Reg) const {
+ExecutionDomainFix::regIndices(MCRegister Reg) const {
   assert(Reg < AliasMap.size() && "Invalid register");
   const auto &Entry = AliasMap[Reg];
   return make_range(Entry.begin(), Entry.end());

llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp

@@ -425,7 +425,7 @@ class StatepointState {
     }
   }
 
-  void insertReloadBefore(unsigned Reg, MachineBasicBlock::iterator It,
+  void insertReloadBefore(Register Reg, MachineBasicBlock::iterator It,
                           MachineBasicBlock *MBB) {
     const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
     int FI = RegToSlotIdx[Reg];

llvm/lib/CodeGen/GlobalISel/Localizer.cpp

@@ -76,7 +76,7 @@ unsigned Localizer::getNumPhiUses(MachineOperand &Op) const {
 bool Localizer::localizeInterBlock(MachineFunction &MF,
                                    LocalizedSetVecT &LocalizedInstrs) {
   bool Changed = false;
-  DenseMap<std::pair<MachineBasicBlock *, unsigned>, unsigned> MBBWithLocalDef;
+  DenseMap<std::pair<MachineBasicBlock *, Register>, Register> MBBWithLocalDef;
 
   // Since the IRTranslator only emits constants into the entry block, and the
   // rest of the GISel pipeline generally emits constants close to their users,
@@ -136,7 +136,7 @@ bool Localizer::localizeInterBlock(MachineFunction &MF,
         Register NewReg = MRI->cloneVirtualRegister(Reg);
         LocalizedMI->getOperand(0).setReg(NewReg);
         NewVRegIt =
-            MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first;
+            MBBWithLocalDef.try_emplace(MBBAndReg, NewReg).first;
         LLVM_DEBUG(dbgs() << "Inserted: " << *LocalizedMI);
       }
       LLVM_DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)

llvm/lib/CodeGen/LiveInterval.cpp

@@ -869,14 +869,14 @@ void LiveInterval::clearSubRanges() {
 /// For each VNI in \p SR, check whether or not that value defines part
 /// of the mask describe by \p LaneMask and if not, remove that value
 /// from \p SR.
-static void stripValuesNotDefiningMask(unsigned Reg, LiveInterval::SubRange &SR,
+static void stripValuesNotDefiningMask(Register Reg, LiveInterval::SubRange &SR,
                                        LaneBitmask LaneMask,
                                        const SlotIndexes &Indexes,
                                        const TargetRegisterInfo &TRI,
                                        unsigned ComposeSubRegIdx) {
   // Phys reg should not be tracked at subreg level.
   // Same for noreg (Reg == 0).
-  if (!Register::isVirtualRegister(Reg) || !Reg)
+  if (!Reg || !Reg.isVirtual())
     return;
   // Remove the values that don't define those lanes.
   SmallVector<VNInfo *, 8> ToBeRemoved;

llvm/lib/CodeGen/LiveRangeCalc.cpp

@@ -83,7 +83,7 @@ void LiveRangeCalc::updateFromLiveIns() {
   LiveIn.clear();
 }
 
-void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, unsigned PhysReg,
+void LiveRangeCalc::extend(LiveRange &LR, SlotIndex Use, Register PhysReg,
                            ArrayRef<SlotIndex> Undefs) {
   assert(Use.isValid() && "Invalid SlotIndex");
   assert(Indexes && "Missing SlotIndexes");
@@ -188,7 +188,7 @@ bool LiveRangeCalc::isDefOnEntry(LiveRange &LR, ArrayRef<SlotIndex> Undefs,
 }
 
 bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
-                                     SlotIndex Use, unsigned PhysReg,
+                                     SlotIndex Use, Register PhysReg,
                                      ArrayRef<SlotIndex> Undefs) {
   unsigned UseMBBNum = UseMBB.getNumber();
 
@@ -216,7 +216,7 @@ bool LiveRangeCalc::findReachingDefs(LiveRange &LR, MachineBasicBlock &UseMBB,
       report_fatal_error("Use not jointly dominated by defs.");
     }
 
-    if (Register::isPhysicalRegister(PhysReg)) {
+    if (PhysReg.isPhysical()) {
       const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
       bool IsLiveIn = MBB->isLiveIn(PhysReg);
       for (MCRegAliasIterator Alias(PhysReg, TRI, false); !IsLiveIn && Alias.isValid(); ++Alias)

llvm/lib/CodeGen/LiveRangeShrink.cpp

@@ -119,7 +119,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
   // register is used last. When moving instructions up, we need to
   // make sure all its defs (including dead def) will not cross its
   // last use when moving up.
-  DenseMap<unsigned, std::pair<unsigned, MachineInstr *>> UseMap;
+  DenseMap<Register, std::pair<unsigned, MachineInstr *>> UseMap;
 
   for (MachineBasicBlock &MBB : MF) {
     if (MBB.empty())

llvm/lib/CodeGen/LiveVariables.cpp

@@ -597,9 +597,9 @@ void LiveVariables::runOnBlock(MachineBasicBlock *MBB, unsigned NumRegs) {
   // if they have PHI nodes, and if so, we simulate an assignment at the end
   // of the current block.
   if (!PHIVarInfo[MBB->getNumber()].empty()) {
-    SmallVectorImpl<unsigned> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
+    SmallVectorImpl<Register> &VarInfoVec = PHIVarInfo[MBB->getNumber()];
 
-    for (unsigned I : VarInfoVec)
+    for (Register I : VarInfoVec)
       // Mark it alive only in the block we are representing.
       MarkVirtRegAliveInBlock(getVarInfo(I), MRI->getVRegDef(I)->getParent(),
                               MBB);

llvm/lib/CodeGen/LocalStackSlotAllocation.cpp

@@ -287,13 +287,11 @@ void LocalStackSlotImpl::calculateFrameObjectOffsets(MachineFunction &Fn) {
   MFI.setLocalFrameMaxAlign(MaxAlign);
 }
 
-static inline bool
-lookupCandidateBaseReg(unsigned BaseReg,
-                       int64_t BaseOffset,
-                       int64_t FrameSizeAdjust,
-                       int64_t LocalFrameOffset,
-                       const MachineInstr &MI,
-                       const TargetRegisterInfo *TRI) {
+static inline bool lookupCandidateBaseReg(Register BaseReg, int64_t BaseOffset,
+                                          int64_t FrameSizeAdjust,
+                                          int64_t LocalFrameOffset,
+                                          const MachineInstr &MI,
+                                          const TargetRegisterInfo *TRI) {
   // Check if the relative offset from the where the base register references
   // to the target address is in range for the instruction.
   int64_t Offset = FrameSizeAdjust + LocalFrameOffset - BaseOffset;

llvm/lib/CodeGen/MachineSSAContext.cpp

@@ -67,7 +67,7 @@ bool MachineSSAContext::isConstantOrUndefValuePhi(const MachineInstr &Phi) {
 
   // In later passes PHI may appear with an undef operand, getVRegDef can fail.
   if (Phi.getOpcode() == TargetOpcode::PHI)
-    return Phi.isConstantValuePHI();
+    return Phi.isConstantValuePHI().isValid();
 
   // For G_PHI we do equivalent of PHINode::hasConstantOrUndefValue().
   const MachineRegisterInfo &MRI = Phi.getMF()->getRegInfo();

llvm/lib/CodeGen/OptimizePHIs.cpp

@@ -44,7 +44,7 @@ class OptimizePHIs {
   using InstrSet = SmallPtrSet<MachineInstr *, 16>;
   using InstrSetIterator = SmallPtrSetIterator<MachineInstr *>;
 
-  bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
+  bool IsSingleValuePHICycle(MachineInstr *MI, Register &SingleValReg,
                              InstrSet &PHIsInCycle);
   bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle);
   bool OptimizeBB(MachineBasicBlock &MBB);
@@ -109,7 +109,7 @@ bool OptimizePHIs::run(MachineFunction &Fn) {
 /// non-copy value. PHIsInCycle is a set used to keep track of the PHIs that
 /// have been scanned. PHIs may be grouped by cycle, several cycles or chains.
 bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI,
-                                         unsigned &SingleValReg,
+                                         Register &SingleValReg,
                                          InstrSet &PHIsInCycle) {
   assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction");
   Register DstReg = MI->getOperand(0).getReg();
@@ -144,7 +144,7 @@ bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI,
         return false;
     } else {
       // Fail if there is more than one non-phi/non-move register.
-      if (SingleValReg != 0 && SingleValReg != SrcReg)
+      if (SingleValReg && SingleValReg != SrcReg)
         return false;
       SingleValReg = SrcReg;
     }
@@ -186,10 +186,9 @@ bool OptimizePHIs::OptimizeBB(MachineBasicBlock &MBB) {
       break;
 
     // Check for single-value PHI cycles.
-    unsigned SingleValReg = 0;
+    Register SingleValReg;
     InstrSet PHIsInCycle;
-    if (IsSingleValuePHICycle(MI, SingleValReg, PHIsInCycle) &&
-        SingleValReg != 0) {
+    if (IsSingleValuePHICycle(MI, SingleValReg, PHIsInCycle) && SingleValReg) {
       Register OldReg = MI->getOperand(0).getReg();
       if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
         continue;

llvm/lib/CodeGen/RenameIndependentSubregs.cpp

@@ -248,7 +248,7 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
       break;
     }
 
-    unsigned VReg = Intervals[ID]->reg();
+    Register VReg = Intervals[ID]->reg();
     MO.setReg(VReg);
 
     if (MO.isTied() && Reg != VReg) {