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[ValueTracking] Ignore poison values in computeKnownBits (#72683)
This patch handles `poison` elements of non-splat vectors in `computeKnownBits`. It addresses test changes after I delete the duplicate logic in #72535. See also @nikic's comment: #72535 (review)
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6 files changed

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-30
lines changed

6 files changed

+30
-30
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‎llvm/lib/Analysis/ValueTracking.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1836,6 +1836,8 @@ void computeKnownBits(const Value *V, const APInt &DemandedElts,
18361836
if (!DemandedElts[i])
18371837
continue;
18381838
Constant *Element = CV->getAggregateElement(i);
1839+
if (isa<PoisonValue>(Element))
1840+
continue;
18391841
auto *ElementCI = dyn_cast_or_null<ConstantInt>(Element);
18401842
if (!ElementCI) {
18411843
Known.resetAll();

‎llvm/test/Transforms/InstCombine/X86/x86-vector-shifts-inseltpoison.ll

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1710,7 +1710,7 @@ define <4 x i64> @avx512_psrav_q_256_allbig(<4 x i64> %v) {
17101710

17111711
define <2 x i64> @avx512_psrav_q_128_poison(<2 x i64> %v) {
17121712
; CHECK-LABEL: @avx512_psrav_q_128_poison(
1713-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 undef, i64 8>
1713+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <2 x i64> [[V:%.*]], <i64 poison, i64 8>
17141714
; CHECK-NEXT: ret <2 x i64> [[TMP1]]
17151715
;
17161716
%1 = insertelement <2 x i64> <i64 0, i64 8>, i64 poison, i64 0
@@ -1720,7 +1720,7 @@ define <2 x i64> @avx512_psrav_q_128_poison(<2 x i64> %v) {
17201720

17211721
define <4 x i64> @avx512_psrav_q_256_poison(<4 x i64> %v) {
17221722
; CHECK-LABEL: @avx512_psrav_q_256_poison(
1723-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
1723+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31>
17241724
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
17251725
;
17261726
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -1756,7 +1756,7 @@ define <8 x i64> @avx512_psrav_q_512_allbig(<8 x i64> %v) {
17561756

17571757
define <8 x i64> @avx512_psrav_q_512_poison(<8 x i64> %v) {
17581758
; CHECK-LABEL: @avx512_psrav_q_512_poison(
1759-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
1759+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
17601760
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
17611761
;
17621762
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -1792,7 +1792,7 @@ define <8 x i16> @avx512_psrav_w_128_allbig(<8 x i16> %v) {
17921792

17931793
define <8 x i16> @avx512_psrav_w_128_poison(<8 x i16> %v) {
17941794
; CHECK-LABEL: @avx512_psrav_w_128_poison(
1795-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
1795+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
17961796
; CHECK-NEXT: ret <8 x i16> [[TMP1]]
17971797
;
17981798
%1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 poison, i64 0
@@ -1828,7 +1828,7 @@ define <16 x i16> @avx512_psrav_w_256_allbig(<16 x i16> %v) {
18281828

18291829
define <16 x i16> @avx512_psrav_w_256_poison(<16 x i16> %v) {
18301830
; CHECK-LABEL: @avx512_psrav_w_256_poison(
1831-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
1831+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
18321832
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
18331833
;
18341834
%1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 poison, i64 0
@@ -1864,7 +1864,7 @@ define <32 x i16> @avx512_psrav_w_512_allbig(<32 x i16> %v) {
18641864

18651865
define <32 x i16> @avx512_psrav_w_512_poison(<32 x i16> %v) {
18661866
; CHECK-LABEL: @avx512_psrav_w_512_poison(
1867-
; CHECK-NEXT: [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
1867+
; CHECK-NEXT: [[TMP1:%.*]] = ashr <32 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
18681868
; CHECK-NEXT: ret <32 x i16> [[TMP1]]
18691869
;
18701870
%1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 poison, i64 0
@@ -1946,7 +1946,7 @@ define <8 x i32> @avx2_psrlv_d_256_allbig(<8 x i32> %v) {
19461946

19471947
define <4 x i32> @avx2_psrlv_d_128_poison(<4 x i32> %v) {
19481948
; CHECK-LABEL: @avx2_psrlv_d_128_poison(
1949-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 undef, i32 8, i32 16, i32 31>
1949+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i32> [[V:%.*]], <i32 poison, i32 8, i32 16, i32 31>
19501950
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
19511951
;
19521952
%1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 poison, i32 0
@@ -1956,7 +1956,7 @@ define <4 x i32> @avx2_psrlv_d_128_poison(<4 x i32> %v) {
19561956

19571957
define <8 x i32> @avx2_psrlv_d_256_poison(<8 x i32> %v) {
19581958
; CHECK-LABEL: @avx2_psrlv_d_256_poison(
1959-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
1959+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
19601960
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
19611961
;
19621962
%1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2045,7 +2045,7 @@ define <2 x i64> @avx2_psrlv_q_128_poison(<2 x i64> %v) {
20452045

20462046
define <4 x i64> @avx2_psrlv_q_256_poison(<4 x i64> %v) {
20472047
; CHECK-LABEL: @avx2_psrlv_q_256_poison(
2048-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
2048+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31>
20492049
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
20502050
;
20512051
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2089,7 +2089,7 @@ define <16 x i32> @avx512_psrlv_d_512_allbig(<16 x i32> %v) {
20892089

20902090
define <16 x i32> @avx512_psrlv_d_512_poison(<16 x i32> %v) {
20912091
; CHECK-LABEL: @avx512_psrlv_d_512_poison(
2092-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
2092+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
20932093
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
20942094
;
20952095
%1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2133,7 +2133,7 @@ define <8 x i64> @avx512_psrlv_q_512_allbig(<8 x i64> %v) {
21332133

21342134
define <8 x i64> @avx512_psrlv_q_512_poison(<8 x i64> %v) {
21352135
; CHECK-LABEL: @avx512_psrlv_q_512_poison(
2136-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
2136+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
21372137
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
21382138
;
21392139
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2177,7 +2177,7 @@ define <8 x i16> @avx512_psrlv_w_128_allbig(<8 x i16> %v) {
21772177

21782178
define <8 x i16> @avx512_psrlv_w_128_poison(<8 x i16> %v) {
21792179
; CHECK-LABEL: @avx512_psrlv_w_128_poison(
2180-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
2180+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
21812181
; CHECK-NEXT: ret <8 x i16> [[TMP1]]
21822182
;
21832183
%1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 poison, i64 0
@@ -2221,7 +2221,7 @@ define <16 x i16> @avx512_psrlv_w_256_allbig(<16 x i16> %v) {
22212221

22222222
define <16 x i16> @avx512_psrlv_w_256_poison(<16 x i16> %v) {
22232223
; CHECK-LABEL: @avx512_psrlv_w_256_poison(
2224-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
2224+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
22252225
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
22262226
;
22272227
%1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 poison, i64 0
@@ -2265,7 +2265,7 @@ define <32 x i16> @avx512_psrlv_w_512_allbig(<32 x i16> %v) {
22652265

22662266
define <32 x i16> @avx512_psrlv_w_512_poison(<32 x i16> %v) {
22672267
; CHECK-LABEL: @avx512_psrlv_w_512_poison(
2268-
; CHECK-NEXT: [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
2268+
; CHECK-NEXT: [[TMP1:%.*]] = lshr <32 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
22692269
; CHECK-NEXT: ret <32 x i16> [[TMP1]]
22702270
;
22712271
%1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 poison, i64 0
@@ -2347,7 +2347,7 @@ define <8 x i32> @avx2_psllv_d_256_allbig(<8 x i32> %v) {
23472347

23482348
define <4 x i32> @avx2_psllv_d_128_poison(<4 x i32> %v) {
23492349
; CHECK-LABEL: @avx2_psllv_d_128_poison(
2350-
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 undef, i32 8, i32 16, i32 31>
2350+
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i32> [[V:%.*]], <i32 poison, i32 8, i32 16, i32 31>
23512351
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
23522352
;
23532353
%1 = insertelement <4 x i32> <i32 0, i32 8, i32 16, i32 31>, i32 poison, i32 0
@@ -2357,7 +2357,7 @@ define <4 x i32> @avx2_psllv_d_128_poison(<4 x i32> %v) {
23572357

23582358
define <8 x i32> @avx2_psllv_d_256_poison(<8 x i32> %v) {
23592359
; CHECK-LABEL: @avx2_psllv_d_256_poison(
2360-
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
2360+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
23612361
; CHECK-NEXT: ret <8 x i32> [[TMP1]]
23622362
;
23632363
%1 = insertelement <8 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2446,7 +2446,7 @@ define <2 x i64> @avx2_psllv_q_128_poison(<2 x i64> %v) {
24462446

24472447
define <4 x i64> @avx2_psllv_q_256_poison(<4 x i64> %v) {
24482448
; CHECK-LABEL: @avx2_psllv_q_256_poison(
2449-
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31>
2449+
; CHECK-NEXT: [[TMP1:%.*]] = shl <4 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31>
24502450
; CHECK-NEXT: ret <4 x i64> [[TMP1]]
24512451
;
24522452
%1 = insertelement <4 x i64> <i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2490,7 +2490,7 @@ define <16 x i32> @avx512_psllv_d_512_allbig(<16 x i32> %v) {
24902490

24912491
define <16 x i32> @avx512_psllv_d_512_poison(<16 x i32> %v) {
24922492
; CHECK-LABEL: @avx512_psllv_d_512_poison(
2493-
; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 0, i32 undef, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
2493+
; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i32> [[V:%.*]], <i32 0, i32 poison, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>
24942494
; CHECK-NEXT: ret <16 x i32> [[TMP1]]
24952495
;
24962496
%1 = insertelement <16 x i32> <i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0, i32 0, i32 8, i32 16, i32 31, i32 31, i32 24, i32 8, i32 0>, i32 poison, i32 1
@@ -2534,7 +2534,7 @@ define <8 x i64> @avx512_psllv_q_512_allbig(<8 x i64> %v) {
25342534

25352535
define <8 x i64> @avx512_psllv_q_512_poison(<8 x i64> %v) {
25362536
; CHECK-LABEL: @avx512_psllv_q_512_poison(
2537-
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 undef, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
2537+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i64> [[V:%.*]], <i64 poison, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>
25382538
; CHECK-NEXT: ret <8 x i64> [[TMP1]]
25392539
;
25402540
%1 = insertelement <8 x i64> <i64 0, i64 8, i64 16, i64 31, i64 0, i64 8, i64 16, i64 31>, i64 poison, i64 0
@@ -2578,7 +2578,7 @@ define <8 x i16> @avx512_psllv_w_128_allbig(<8 x i16> %v) {
25782578

25792579
define <8 x i16> @avx512_psllv_w_128_poison(<8 x i16> %v) {
25802580
; CHECK-LABEL: @avx512_psllv_w_128_poison(
2581-
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
2581+
; CHECK-NEXT: [[TMP1:%.*]] = shl <8 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
25822582
; CHECK-NEXT: ret <8 x i16> [[TMP1]]
25832583
;
25842584
%1 = insertelement <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, i16 poison, i64 0
@@ -2622,7 +2622,7 @@ define <16 x i16> @avx512_psllv_w_256_allbig(<16 x i16> %v) {
26222622

26232623
define <16 x i16> @avx512_psllv_w_256_poison(<16 x i16> %v) {
26242624
; CHECK-LABEL: @avx512_psllv_w_256_poison(
2625-
; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
2625+
; CHECK-NEXT: [[TMP1:%.*]] = shl <16 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
26262626
; CHECK-NEXT: ret <16 x i16> [[TMP1]]
26272627
;
26282628
%1 = insertelement <16 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>, i16 poison, i64 0
@@ -2666,7 +2666,7 @@ define <32 x i16> @avx512_psllv_w_512_allbig(<32 x i16> %v) {
26662666

26672667
define <32 x i16> @avx512_psllv_w_512_poison(<32 x i16> %v) {
26682668
; CHECK-LABEL: @avx512_psllv_w_512_poison(
2669-
; CHECK-NEXT: [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 undef, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
2669+
; CHECK-NEXT: [[TMP1:%.*]] = shl <32 x i16> [[V:%.*]], <i16 poison, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>
26702670
; CHECK-NEXT: ret <32 x i16> [[TMP1]]
26712671
;
26722672
%1 = insertelement <32 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 15, i16 14, i16 13, i16 12, i16 11, i16 10, i16 9, i16 8, i16 7, i16 6, i16 5, i16 4, i16 3, i16 2, i16 1, i16 0>, i16 poison, i64 0

‎llvm/test/Transforms/InstCombine/add.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3037,7 +3037,7 @@ define <2 x i32> @dec_zext_add_nonzero_vec_poison2(<2 x i8> %x) {
30373037
; CHECK-NEXT: [[O:%.*]] = or <2 x i8> [[X:%.*]], <i8 8, i8 8>
30383038
; CHECK-NEXT: [[A:%.*]] = add nsw <2 x i8> [[O]], <i8 -1, i8 -1>
30393039
; CHECK-NEXT: [[B:%.*]] = zext <2 x i8> [[A]] to <2 x i32>
3040-
; CHECK-NEXT: [[C:%.*]] = add <2 x i32> [[B]], <i32 1, i32 poison>
3040+
; CHECK-NEXT: [[C:%.*]] = add nuw nsw <2 x i32> [[B]], <i32 1, i32 poison>
30413041
; CHECK-NEXT: ret <2 x i32> [[C]]
30423042
;
30433043
%o = or <2 x i8> %x, <i8 8, i8 8>

‎llvm/test/Transforms/InstCombine/extractelement.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -819,7 +819,7 @@ define i32 @extelt_select_const_operand_select_use(i1 %c) {
819819
; ANY-NEXT: [[S:%.*]] = select i1 [[C:%.*]], <3 x i32> <i32 poison, i32 3, i32 4>, <3 x i32> <i32 poison, i32 6, i32 7>
820820
; ANY-NEXT: [[E:%.*]] = extractelement <3 x i32> [[S]], i64 2
821821
; ANY-NEXT: [[E_2:%.*]] = extractelement <3 x i32> [[S]], i64 1
822-
; ANY-NEXT: [[R:%.*]] = mul i32 [[E]], [[E_2]]
822+
; ANY-NEXT: [[R:%.*]] = mul nuw nsw i32 [[E]], [[E_2]]
823823
; ANY-NEXT: ret i32 [[R]]
824824
;
825825
%s = select i1 %c, <3 x i32> <i32 2, i32 3, i32 4>, <3 x i32> <i32 5, i32 6, i32 7>

‎llvm/test/Transforms/InstCombine/lshr.ll

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -889,13 +889,11 @@ define <2 x i64> @narrow_bswap_splat(<2 x i16> %x) {
889889
ret <2 x i64> %s
890890
}
891891

892-
; TODO: poison/undef in the shift amount is ok to propagate.
893-
894892
define <2 x i64> @narrow_bswap_splat_poison_elt(<2 x i16> %x) {
895893
; CHECK-LABEL: @narrow_bswap_splat_poison_elt(
896894
; CHECK-NEXT: [[Z:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i64>
897895
; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> [[Z]])
898-
; CHECK-NEXT: [[S:%.*]] = lshr <2 x i64> [[B]], <i64 48, i64 poison>
896+
; CHECK-NEXT: [[S:%.*]] = lshr exact <2 x i64> [[B]], <i64 48, i64 poison>
899897
; CHECK-NEXT: ret <2 x i64> [[S]]
900898
;
901899
%z = zext <2 x i16> %x to <2 x i64>

‎llvm/test/Transforms/InstCombine/mul.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -981,8 +981,8 @@ define <2 x i32> @PR57278_shl_vec(<2 x i32> %v1) {
981981
define <2 x i32> @PR57278_shl_vec_poison(<2 x i32> %v1) {
982982
; CHECK-LABEL: @PR57278_shl_vec_poison(
983983
; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i32> [[V1:%.*]], <i32 2, i32 poison>
984-
; CHECK-NEXT: [[ADD:%.*]] = or <2 x i32> [[SHL]], <i32 3, i32 poison>
985-
; CHECK-NEXT: [[MUL:%.*]] = mul nuw <2 x i32> [[ADD]], <i32 3, i32 poison>
984+
; CHECK-NEXT: [[TMP1:%.*]] = mul nuw <2 x i32> [[SHL]], <i32 3, i32 poison>
985+
; CHECK-NEXT: [[MUL:%.*]] = add nuw <2 x i32> [[TMP1]], <i32 9, i32 poison>
986986
; CHECK-NEXT: ret <2 x i32> [[MUL]]
987987
;
988988
%shl = shl nuw <2 x i32> %v1, <i32 2, i32 poison>
@@ -1765,7 +1765,7 @@ define <2 x i16> @sext_negpow2_vec(<2 x i8> %x) {
17651765
define <2 x i16> @sext_negpow2_too_small_vec(<2 x i8> %x) {
17661766
; CHECK-LABEL: @sext_negpow2_too_small_vec(
17671767
; CHECK-NEXT: [[SX:%.*]] = sext <2 x i8> [[X:%.*]] to <2 x i16>
1768-
; CHECK-NEXT: [[R:%.*]] = mul <2 x i16> [[SX]], <i16 -128, i16 poison>
1768+
; CHECK-NEXT: [[R:%.*]] = mul nsw <2 x i16> [[SX]], <i16 -128, i16 poison>
17691769
; CHECK-NEXT: ret <2 x i16> [[R]]
17701770
;
17711771
%sx = sext <2 x i8> %x to <2 x i16>

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