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1 | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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2 | 2 | ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=SI %s
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3 | 3 | ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=VI %s
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4 |
| -; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11 %s |
| 4 | +; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=+real-true16,-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11 %s |
5 | 5 | ; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs -enable-misched=false < %s | FileCheck -check-prefixes=GFX11-FAKE16 %s
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6 | 6 |
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7 | 7 | define amdgpu_kernel void @fadd_f16(
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@@ -74,7 +74,9 @@ define amdgpu_kernel void @fadd_f16(
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74 | 74 | ; GFX11-NEXT: s_waitcnt vmcnt(0)
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75 | 75 | ; GFX11-NEXT: buffer_load_u16 v1, off, s[0:3], 0 glc dlc
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76 | 76 | ; GFX11-NEXT: s_waitcnt vmcnt(0)
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77 |
| -; GFX11-NEXT: v_add_f16_e32 v0, v0, v1 |
| 77 | +; GFX11-NEXT: v_mov_b16_e32 v0.h, v1.l |
| 78 | +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| 79 | +; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h |
78 | 80 | ; GFX11-NEXT: buffer_store_b16 v0, off, s[8:11], 0
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79 | 81 | ; GFX11-NEXT: s_nop 0
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80 | 82 | ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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@@ -169,7 +171,9 @@ define amdgpu_kernel void @fadd_f16_imm_a(
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169 | 171 | ; GFX11-NEXT: s_mov_b32 s3, s7
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170 | 172 | ; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0
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171 | 173 | ; GFX11-NEXT: s_waitcnt vmcnt(0)
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172 |
| -; GFX11-NEXT: v_add_f16_e32 v0, 1.0, v0 |
| 174 | +; GFX11-NEXT: v_mov_b16_e32 v0.h, 0x3c00 |
| 175 | +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| 176 | +; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h |
173 | 177 | ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
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174 | 178 | ; GFX11-NEXT: s_nop 0
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175 | 179 | ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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@@ -256,7 +260,9 @@ define amdgpu_kernel void @fadd_f16_imm_b(
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256 | 260 | ; GFX11-NEXT: s_mov_b32 s3, s7
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257 | 261 | ; GFX11-NEXT: buffer_load_u16 v0, off, s[0:3], 0
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258 | 262 | ; GFX11-NEXT: s_waitcnt vmcnt(0)
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259 |
| -; GFX11-NEXT: v_add_f16_e32 v0, 2.0, v0 |
| 263 | +; GFX11-NEXT: v_mov_b16_e32 v0.h, 0x4000 |
| 264 | +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| 265 | +; GFX11-NEXT: v_add_f16_e32 v0.l, v0.l, v0.h |
260 | 266 | ; GFX11-NEXT: buffer_store_b16 v0, off, s[4:7], 0
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261 | 267 | ; GFX11-NEXT: s_nop 0
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262 | 268 | ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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