[M68k](3/8) Skeleton and target description files

 - Infrastructure for the target (i.e. build files, target triple etc.)
 - All of the target description TableGen file

Authors: myhsu, m4yers, glaubitz

Differential Revision: https://reviews.llvm.org/D88389

Author: mshockwave

llvm/cmake/config-ix.cmake

@@ -452,6 +452,8 @@ elseif (LLVM_NATIVE_ARCH MATCHES "riscv32")
   set(LLVM_NATIVE_ARCH RISCV)
 elseif (LLVM_NATIVE_ARCH MATCHES "riscv64")
   set(LLVM_NATIVE_ARCH RISCV)
+elseif (LLVM_NATIVE_ARCH STREQUAL "m68k")
+  set(LLVM_NATIVE_ARCH M68k)
 else ()
   message(FATAL_ERROR "Unknown architecture ${LLVM_NATIVE_ARCH}")
 endif ()

llvm/include/llvm/ADT/Triple.h

@@ -58,6 +58,7 @@ class Triple {
     bpfeb,          // eBPF or extended BPF or 64-bit BPF (big endian)
     csky,           // CSKY: csky
     hexagon,        // Hexagon: hexagon
+    m68k,           // M68k: Motorola 680x0 family
     mips,           // MIPS: mips, mipsallegrex, mipsr6
     mipsel,         // MIPSEL: mipsel, mipsallegrexe, mipsr6el
     mips64,         // MIPS64: mips64, mips64r6, mipsn32, mipsn32r6

llvm/lib/Support/Triple.cpp

@@ -44,6 +44,7 @@ StringRef Triple::getArchTypeName(ArchType Kind) {
   case lanai:          return "lanai";
   case le32:           return "le32";
   case le64:           return "le64";
+  case m68k:           return "m68k";
   case mips64:         return "mips64";
   case mips64el:       return "mips64el";
   case mips:           return "mips";
@@ -105,6 +106,8 @@ StringRef Triple::getArchTypePrefix(ArchType Kind) {
   case ppc:
   case ppcle:       return "ppc";
 
+  case m68k:        return "m68k";
+
   case mips:
   case mipsel:
   case mips64:
@@ -281,6 +284,7 @@ Triple::ArchType Triple::getArchTypeForLLVMName(StringRef Name) {
     .Case("armeb", armeb)
     .Case("avr", avr)
     .StartsWith("bpf", BPFArch)
+    .Case("m68k", m68k)
     .Case("mips", mips)
     .Case("mipsel", mipsel)
     .Case("mips64", mips64)
@@ -419,6 +423,7 @@ static Triple::ArchType parseArch(StringRef ArchName) {
     .Case("thumb", Triple::thumb)
     .Case("thumbeb", Triple::thumbeb)
     .Case("avr", Triple::avr)
+    .Case("m68k", Triple::m68k)
     .Case("msp430", Triple::msp430)
     .Cases("mips", "mipseb", "mipsallegrex", "mipsisa32r6",
            "mipsr6", Triple::mips)
@@ -704,6 +709,7 @@ static Triple::ObjectFormatType getDefaultFormat(const Triple &T) {
   case Triple::lanai:
   case Triple::le32:
   case Triple::le64:
+  case Triple::m68k:
   case Triple::mips64:
   case Triple::mips64el:
   case Triple::mips:
@@ -1277,6 +1283,7 @@ static unsigned getArchPointerBitWidth(llvm::Triple::ArchType Arch) {
   case llvm::Triple::kalimba:
   case llvm::Triple::lanai:
   case llvm::Triple::le32:
+  case llvm::Triple::m68k:
   case llvm::Triple::mips:
   case llvm::Triple::mipsel:
   case llvm::Triple::nvptx:
@@ -1361,6 +1368,7 @@ Triple Triple::get32BitArchVariant() const {
   case Triple::kalimba:
   case Triple::lanai:
   case Triple::le32:
+  case Triple::m68k:
   case Triple::mips:
   case Triple::mipsel:
   case Triple::nvptx:
@@ -1413,6 +1421,7 @@ Triple Triple::get64BitArchVariant() const {
   case Triple::hexagon:
   case Triple::kalimba:
   case Triple::lanai:
+  case Triple::m68k:
   case Triple::msp430:
   case Triple::r600:
   case Triple::shave:
@@ -1537,6 +1546,7 @@ Triple Triple::getLittleEndianArchVariant() const {
   case Triple::lanai:
   case Triple::sparcv9:
   case Triple::systemz:
+  case Triple::m68k:
 
   // ARM is intentionally unsupported here, changing the architecture would
   // drop any arch suffixes.

llvm/lib/Target/M68k/CMakeLists.txt

@@ -0,0 +1,36 @@
+add_llvm_component_group(M68k)
+
+set(LLVM_TARGET_DEFINITIONS M68k.td)
+
+tablegen(LLVM M68kGenRegisterInfo.inc     -gen-register-info)
+tablegen(LLVM M68kGenInstrInfo.inc        -gen-instr-info)
+tablegen(LLVM M68kGenSubtargetInfo.inc    -gen-subtarget)
+tablegen(LLVM M68kGenMCCodeBeads.inc      -gen-code-beads)
+tablegen(LLVM M68kGenMCPseudoLowering.inc -gen-pseudo-lowering)
+tablegen(LLVM M68kGenDAGISel.inc          -gen-dag-isel)
+tablegen(LLVM M68kGenCallingConv.inc      -gen-callingconv)
+tablegen(LLVM M68kGenAsmWriter.inc        -gen-asm-writer)
+
+add_public_tablegen_target(M68kCommonTableGen)
+
+add_llvm_target(M68kCodeGen
+  M68kTargetMachine.cpp
+
+  LINK_COMPONENTS
+  Analysis
+  AsmPrinter
+  CodeGen
+  Core
+  MC
+  SelectionDAG
+  Support
+  Target
+  M68kDesc
+  M68kInfo
+
+  ADD_TO_COMPONENT
+  M68k
+)
+
+add_subdirectory(TargetInfo)
+add_subdirectory(MCTargetDesc)

llvm/lib/Target/M68k/M68k.td

@@ -0,0 +1,93 @@
+//===-- M68k.td - Motorola 680x0 target definitions ------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This is a target description file for the Motorola 680x0 family, referred
+/// to here as the "M68k" architecture.
+///
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// M68k Subtarget features
+//===----------------------------------------------------------------------===//
+
+def FeatureISA00
+  : SubtargetFeature<"isa-68000", "SubtargetKind", "M00",
+                     "Is M68000 ISA supported">;
+
+def FeatureISA10
+  : SubtargetFeature<"isa-68010", "SubtargetKind", "M10",
+                     "Is M68010 ISA supported",
+                     [ FeatureISA00 ]>;
+
+def FeatureISA20
+  : SubtargetFeature<"isa-68020", "SubtargetKind", "M20",
+                     "Is M68020 ISA supported",
+                     [ FeatureISA10 ]>;
+
+def FeatureISA30
+  : SubtargetFeature<"isa-68030", "SubtargetKind", "M30",
+                     "Is M68030 ISA supported",
+                     [ FeatureISA20 ]>;
+
+def FeatureISA40
+  : SubtargetFeature<"isa-68040", "SubtargetKind", "M40",
+                     "Is M68040 ISA supported",
+                     [ FeatureISA30 ]>;
+
+def FeatureISA60
+  : SubtargetFeature<"isa-68060", "SubtargetKind", "M60",
+                     "Is M68060 ISA supported",
+                     [ FeatureISA40 ]>;
+
+//===----------------------------------------------------------------------===//
+// M68k processors supported.
+//===----------------------------------------------------------------------===//
+
+include "M68kSchedule.td"
+
+class Proc<string Name, list<SubtargetFeature> Features>
+    : ProcessorModel<Name, GenericM68kModel, Features>;
+
+def : Proc<"generic", [ FeatureISA00 ]>;
+def : Proc<"M68000",  [ FeatureISA00 ]>;
+def : Proc<"M68010",  [ FeatureISA10 ]>;
+def : Proc<"M68020",  [ FeatureISA20 ]>;
+def : Proc<"M68030",  [ FeatureISA30 ]>;
+def : Proc<"M68040",  [ FeatureISA40 ]>;
+def : Proc<"M68060",  [ FeatureISA60 ]>;
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "M68kRegisterInfo.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+include "M68kInstrInfo.td"
+
+def M68kInstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// Calling Conventions
+//===----------------------------------------------------------------------===//
+
+include "M68kCallingConv.td"
+
+//===----------------------------------------------------------------------===//
+// Target
+//===----------------------------------------------------------------------===//
+
+def M68k : Target {
+  let InstructionSet = M68kInstrInfo;
+}

llvm/lib/Target/M68k/M68kCallingConv.td

@@ -0,0 +1,119 @@
+//===-- M68kCallingConv.td - Calling Conventions for M68k --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This describes the calling conventions for the M68k architectures. These
+/// conventions assume Int to be 4 bytes and 4 byte aligned.
+///
+//===----------------------------------------------------------------------===//
+
+// TODO Verify C convention follows SysV M68K ABI
+
+class CCIfSubtarget<string F, CCAction A>
+    : CCIf<!strconcat("static_cast<const M68kSubtarget &>"
+                      "(State.getMachineFunction().getSubtarget()).", F), A>;
+
+//===----------------------------------------------------------------------===//
+// Return Value Calling Conventions
+//===----------------------------------------------------------------------===//
+
+/// Return-value conventions common to all M68k CC's.
+def RetCC_M68kCommon : CallingConv<[
+]>;
+
+/// M68k C return convention.
+/// TODO: Return via address register
+def RetCC_M68k_C : CallingConv<[
+  CCIfType<[i1],   CCPromoteToType<i8>>,
+  CCIfType<[i8],   CCAssignToReg<[BD0, BD1]>>,
+  CCIfType<[i16],  CCAssignToReg<[WD0, WD1]>>,
+  CCIfType<[i32],  CCAssignToReg<[D0, D1]>>,
+  CCDelegateTo<RetCC_M68kCommon>
+]>;
+
+/// M68k fastcc return convention.
+/// This convention allows to return up to 16 bytes in registers which can be
+/// split among 16 1-byte values or used for a single 16-byte value.
+/// TODO: Verify its functionality and write tests
+def RetCC_M68k_Fast : CallingConv<[
+  CCIfType<[i1],   CCPromoteToType<i8>>,
+  CCIfType<[i8],   CCAssignToReg<[BD0, BD1]>>,
+  CCIfType<[i16],  CCAssignToReg<[WD0, WD1, WA0, WA1]>>,
+  CCIfType<[i32],  CCAssignToReg<[D0, D1, A0, A1]>>,
+  CCDelegateTo<RetCC_M68kCommon>
+]>;
+
+/// This is the root return-value convention for the M68k backend.
+def RetCC_M68k : CallingConv<[
+  CCIfCC<"CallingConv::Fast", CCDelegateTo<RetCC_M68k_Fast>>,
+  CCDelegateTo<RetCC_M68k_C>
+]>;
+
+//===----------------------------------------------------------------------===//
+// M68k C Calling Convention
+//===----------------------------------------------------------------------===//
+
+/// CC_M68k_Common - In all M68k calling conventions, extra integers and FP
+/// values are spilled on the stack.
+def CC_M68k_Common : CallingConv<[
+  /// Handles byval parameters.
+  CCIfByVal<CCPassByVal<4, 4>>,
+
+  /// Integer values get stored in stack slots that are 4 bytes in
+  /// size and 4-byte aligned.
+  CCIfType<[i32],  CCAssignToStack<4, 4>>
+]>;
+
+def CC_M68k_Fast : CallingConv<[
+  /// Promote i1/i8/i16 arguments to i32.
+  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+
+  /// The 'nest' parameter, if any, is passed in A1.
+  CCIfNest<CCAssignToReg<[A1]>>, // FIXME verify if this is correct
+
+  /// Since M68k uses %An for pointers and we want them be passed in regs
+  /// too we have to use custom function.
+  CCIfType<[i32], CCCustom<"CC_M68k_Any_AssignToReg">>,
+
+  /// Otherwise, same as everything else.
+  CCDelegateTo<CC_M68k_Common>
+]>;
+
+def CC_M68k_C : CallingConv<[
+  /// Promote i1/i8/i16 arguments to i32.
+  CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
+
+  /// The 'nest' parameter, if any, is passed in A1.
+  CCIfNest<CCAssignToReg<[A1]>>, // FIXME verify if this is correct
+
+  /// Use registers only if 'inreg' used and the call is not vararg
+  CCIfNotVarArg<CCIfInReg<CCIfType<[i32], CCAssignToReg<[D0, D1]>>>>,
+
+  // TODO: Support for 'sret'
+
+  /// Otherwise, same as everything else.
+  CCDelegateTo<CC_M68k_Common>
+]>;
+
+/// This is the root argument convention for the M68k backend.
+def CC_M68k : CallingConv<[
+  CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_M68k_Fast>>,
+  CCDelegateTo<CC_M68k_C>
+]>;
+
+//===----------------------------------------------------------------------===//
+// Callee-saved Registers.
+//===----------------------------------------------------------------------===//
+
+def CSR_NoRegs : CalleeSavedRegs<(add)>;
+
+// A5 - BP
+// A6 - FP
+def CSR_STD : CalleeSavedRegs<(add D2, D3, D4, D5, D6, D7,
+                                   A2, A3, A4, A5, A6)>;
+