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jiahanxie353 · jiahanxie353 · commit bec85ab15c3b · 2024-01-11T19:55:56.000-05:00
diff --git a/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp b/llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
@@ -277,7 +277,8 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
     }
 
     const LLT Ty = MRI.getType(VReg);
-    if (Ty.isValid() && TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
+    if (Ty.isValid() &&
+        TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {
       reportGISelFailure(
           MF, TPC, MORE, "gisel-select",
           "VReg's low-level type and register class have different sizes", *MI);

Original file line number	Diff line number	Diff line change
`@@ -277,7 +277,8 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {`
`277`	`277`	`}`
`278`	`278`
`279`	`279`	`const LLT Ty = MRI.getType(VReg);`
`280`		`- if (Ty.isValid() && TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {`
	`280`	`+ if (Ty.isValid() &&`
	`281`	`+ TypeSize::isKnownGT(Ty.getSizeInBits(), TRI.getRegSizeInBits(*RC))) {`
`281`	`282`	`reportGISelFailure(`
`282`	`283`	`MF, TPC, MORE, "gisel-select",`
`283`	`284`	`"VReg's low-level type and register class have different sizes", *MI);`