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Kai Luo
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[PowerPC] Adjust operand order of ADDItoc to be consistent with other ADDI* nodes (#93642)
Simultaneously, the `ADDItoc` machineinstr is generated in `PPCISelDAGToDAG::Select` so the pattern is not used and can be removed.
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7 files changed

+129
-69
lines changed

7 files changed

+129
-69
lines changed

‎llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1079,13 +1079,13 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
10791079
assert(IsAIX && TM.getCodeModel() == CodeModel::Small &&
10801080
"PseudoOp only valid for small code model AIX");
10811081

1082-
// Transform %rN = ADDItoc/8 @op1, %r2.
1082+
// Transform %rN = ADDItoc/8 %r2, @op1.
10831083
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
10841084

10851085
// Change the opcode to load address.
10861086
TmpInst.setOpcode((!IsPPC64) ? (PPC::LA) : (PPC::LA8));
10871087

1088-
const MachineOperand &MO = MI->getOperand(1);
1088+
const MachineOperand &MO = MI->getOperand(2);
10891089
assert(MO.isGlobal() && "Invalid operand for ADDItoc[8].");
10901090

10911091
// Map the operand to its corresponding MCSymbol.
@@ -1094,7 +1094,6 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr *MI) {
10941094
const MCExpr *Exp =
10951095
MCSymbolRefExpr::create(MOSymbol, MCSymbolRefExpr::VK_None, OutContext);
10961096

1097-
TmpInst.getOperand(1) = TmpInst.getOperand(2);
10981097
TmpInst.getOperand(2) = MCOperand::createExpr(Exp);
10991098
EmitToStreamer(*OutStreamer, TmpInst);
11001099
return;

‎llvm/lib/Target/PowerPC/PPCFastISel.cpp

Lines changed: 9 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2080,13 +2080,15 @@ unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
20802080
cast<GlobalVariable>(GV)->hasAttribute("toc-data");
20812081

20822082
// For small code model, generate a simple TOC load.
2083-
if (CModel == CodeModel::Small)
2084-
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2085-
IsAIXTocData ? TII.get(PPC::ADDItoc8) : TII.get(PPC::LDtoc),
2086-
DestReg)
2087-
.addGlobalAddress(GV)
2088-
.addReg(PPC::X2);
2089-
else {
2083+
if (CModel == CodeModel::Small) {
2084+
auto MIB = BuildMI(
2085+
*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
2086+
IsAIXTocData ? TII.get(PPC::ADDItoc8) : TII.get(PPC::LDtoc), DestReg);
2087+
if (IsAIXTocData)
2088+
MIB.addReg(PPC::X2).addGlobalAddress(GV);
2089+
else
2090+
MIB.addGlobalAddress(GV).addReg(PPC::X2);
2091+
} else {
20902092
// If the address is an externally defined symbol, a symbol with common
20912093
// or externally available linkage, a non-local function address, or a
20922094
// jump table address (not yet needed), or if we are generating code

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6102,8 +6102,15 @@ void PPCDAGToDAGISel::Select(SDNode *N) {
61026102
EVT OperandTy) {
61036103
SDValue GA = TocEntry->getOperand(0);
61046104
SDValue TocBase = TocEntry->getOperand(1);
6105-
SDNode *MN = CurDAG->getMachineNode(OpCode, dl, OperandTy, GA, TocBase);
6106-
transferMemOperands(TocEntry, MN);
6105+
SDNode *MN = nullptr;
6106+
if (OpCode == PPC::ADDItoc || OpCode == PPC::ADDItoc8)
6107+
// toc-data access doesn't involve in loading from got, no need to
6108+
// keep memory operands.
6109+
MN = CurDAG->getMachineNode(OpCode, dl, OperandTy, TocBase, GA);
6110+
else {
6111+
MN = CurDAG->getMachineNode(OpCode, dl, OperandTy, GA, TocBase);
6112+
transferMemOperands(TocEntry, MN);
6113+
}
61076114
ReplaceNode(TocEntry, MN);
61086115
};
61096116

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1485,11 +1485,9 @@ def ADDItocL8: PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:
14851485
}
14861486

14871487
// Local Data Transform
1488-
def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
1488+
def ADDItoc8 : PPCEmitTimePseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
14891489
"#ADDItoc8",
1490-
[(set i64:$rD,
1491-
(PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
1492-
1490+
[]>, isPPC64;
14931491
let mayLoad = 1 in
14941492
def LDtocL: PPCEmitTimePseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
14951493
"#LDtocL", []>, isPPC64;

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3345,10 +3345,8 @@ def LWZtocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc_nor
33453345
def ADDIStocHA : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
33463346
"#ADDIStocHA", []>;
33473347
// TOC Data Transform on AIX
3348-
def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins tocentry32:$disp, gprc:$reg),
3349-
"#ADDItoc",
3350-
[(set i32:$rD,
3351-
(PPCtoc_entry tglobaladdr:$disp, i32:$reg))]>;
3348+
def ADDItoc : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc:$reg, tocentry32:$disp),
3349+
"#ADDItoc", []>;
33523350
def ADDItocL : PPCEmitTimePseudo<(outs gprc:$rD), (ins gprc_nor0:$reg, tocentry32:$disp),
33533351
"#ADDItocL", []>;
33543352

‎llvm/test/CodeGen/PowerPC/toc-data-common.ll

Lines changed: 96 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s -DINSTR=lwz --check-prefix=CHECK
3-
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s -DINSTR=ld --check-prefix=CHECK
2+
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK
3+
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-64
44

55
; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o
66
; RUN: llvm-objdump -t --symbol-description %t32.o | FileCheck %s --check-prefix=OBJ32
@@ -15,16 +15,28 @@
1515

1616
define void @set(i32 noundef %_a) {
1717
; CHECK-LABEL: set:
18-
; CHECK: # %bb.0: # %entry
19-
; CHECK-NEXT: la 4, a2[TD](2)
20-
; CHECK-NEXT: la 5, a1[TD](2)
21-
; CHECK-NEXT: stw 3, 0(4)
22-
; CHECK-NEXT: [[INSTR]] 4, L..C0(2) # @a4
23-
; CHECK-NEXT: stw 3, 0(5)
24-
; CHECK-NEXT: [[INSTR]] 5, L..C1(2) # @a3
25-
; CHECK-NEXT: stw 3, 0(4)
26-
; CHECK-NEXT: stw 3, 0(5)
27-
; CHECK-NEXT: blr
18+
; CHECK: # %bb.0: # %entry
19+
; CHECK-NEXT: la 4, a2[TD](2)
20+
; CHECK-NEXT: lwz 5, L..C0(2) # @a4
21+
; CHECK-NEXT: stw 3, 0(4)
22+
; CHECK-NEXT: la 4, a1[TD](2)
23+
; CHECK-NEXT: stw 3, 0(4)
24+
; CHECK-NEXT: lwz 4, L..C1(2) # @a3
25+
; CHECK-NEXT: stw 3, 0(5)
26+
; CHECK-NEXT: stw 3, 0(4)
27+
; CHECK-NEXT: blr
28+
;
29+
; CHECK-64-LABEL: set:
30+
; CHECK-64: # %bb.0: # %entry
31+
; CHECK-64-NEXT: la 4, a2[TD](2)
32+
; CHECK-64-NEXT: ld 5, L..C0(2) # @a4
33+
; CHECK-64-NEXT: stw 3, 0(4)
34+
; CHECK-64-NEXT: la 4, a1[TD](2)
35+
; CHECK-64-NEXT: stw 3, 0(4)
36+
; CHECK-64-NEXT: ld 4, L..C1(2) # @a3
37+
; CHECK-64-NEXT: stw 3, 0(5)
38+
; CHECK-64-NEXT: stw 3, 0(4)
39+
; CHECK-64-NEXT: blr
2840
entry:
2941
store i32 %_a, ptr @a2, align 4
3042
store i32 %_a, ptr @a1, align 4
@@ -35,80 +47,124 @@ ret void
3547

3648
define i32 @get1() {
3749
; CHECK-LABEL: get1:
38-
; CHECK: # %bb.0: # %entry
39-
; CHECK-NEXT: la 3, a2[TD](2)
40-
; CHECK-NEXT: lwz 3, 0(3)
41-
; CHECK-NEXT: blr
50+
; CHECK: # %bb.0: # %entry
51+
; CHECK-NEXT: la 3, a2[TD](2)
52+
; CHECK-NEXT: lwz 3, 0(3)
53+
; CHECK-NEXT: blr
54+
;
55+
; CHECK-64-LABEL: get1:
56+
; CHECK-64: # %bb.0: # %entry
57+
; CHECK-64-NEXT: la 3, a2[TD](2)
58+
; CHECK-64-NEXT: lwz 3, 0(3)
59+
; CHECK-64-NEXT: blr
4260
entry:
4361
%0 = load i32, ptr @a2, align 4
4462
ret i32 %0
4563
}
4664

4765
define i32 @get2() {
4866
; CHECK-LABEL: get2:
49-
; CHECK: # %bb.0: # %entry
50-
; CHECK-NEXT: la 3, a1[TD](2)
51-
; CHECK-NEXT: lwz 3, 0(3)
52-
; CHECK-NEXT: blr
67+
; CHECK: # %bb.0: # %entry
68+
; CHECK-NEXT: la 3, a1[TD](2)
69+
; CHECK-NEXT: lwz 3, 0(3)
70+
; CHECK-NEXT: blr
71+
;
72+
; CHECK-64-LABEL: get2:
73+
; CHECK-64: # %bb.0: # %entry
74+
; CHECK-64-NEXT: la 3, a1[TD](2)
75+
; CHECK-64-NEXT: lwz 3, 0(3)
76+
; CHECK-64-NEXT: blr
5377
entry:
5478
%0 = load i32, ptr @a1, align 4
5579
ret i32 %0
5680
}
5781

5882
define i32 @get3() {
5983
; CHECK-LABEL: get3:
60-
; CHECK: # %bb.0: # %entry
61-
; CHECK-NEXT: [[INSTR]] 3, L..C0(2) # @a4
62-
; CHECK-NEXT: lwz 3, 0(3)
63-
; CHECK-NEXT: blr
84+
; CHECK: # %bb.0: # %entry
85+
; CHECK-NEXT: lwz 3, L..C0(2) # @a4
86+
; CHECK-NEXT: lwz 3, 0(3)
87+
; CHECK-NEXT: blr
88+
;
89+
; CHECK-64-LABEL: get3:
90+
; CHECK-64: # %bb.0: # %entry
91+
; CHECK-64-NEXT: ld 3, L..C0(2) # @a4
92+
; CHECK-64-NEXT: lwz 3, 0(3)
93+
; CHECK-64-NEXT: blr
6494
entry:
6595
%0 = load i32, ptr @a4, align 4
6696
ret i32 %0
6797
}
6898

6999
define i32 @get4() {
70100
; CHECK-LABEL: get4:
71-
; CHECK: # %bb.0: # %entry
72-
; CHECK-NEXT: [[INSTR]] 3, L..C1(2) # @a3
73-
; CHECK-NEXT: lwz 3, 0(3)
74-
; CHECK-NEXT: blr
101+
; CHECK: # %bb.0: # %entry
102+
; CHECK-NEXT: lwz 3, L..C1(2) # @a3
103+
; CHECK-NEXT: lwz 3, 0(3)
104+
; CHECK-NEXT: blr
105+
;
106+
; CHECK-64-LABEL: get4:
107+
; CHECK-64: # %bb.0: # %entry
108+
; CHECK-64-NEXT: ld 3, L..C1(2) # @a3
109+
; CHECK-64-NEXT: lwz 3, 0(3)
110+
; CHECK-64-NEXT: blr
75111
entry:
76112
%0 = load i32, ptr @a3, align 4
77113
ret i32 %0
78114
}
79115

80116
define nonnull ptr @escape1() {
81117
; CHECK-LABEL: escape1:
82-
; CHECK: # %bb.0: # %entry
83-
; CHECK-NEXT: la 3, a2[TD](2)
84-
; CHECK-NEXT: blr
118+
; CHECK: # %bb.0: # %entry
119+
; CHECK-NEXT: la 3, a2[TD](2)
120+
; CHECK-NEXT: blr
121+
;
122+
; CHECK-64-LABEL: escape1:
123+
; CHECK-64: # %bb.0: # %entry
124+
; CHECK-64-NEXT: la 3, a2[TD](2)
125+
; CHECK-64-NEXT: blr
85126
entry:
86127
ret ptr @a2
87128
}
88129

89130
define nonnull ptr @escape2() {
90131
; CHECK-LABEL: escape2:
91-
; CHECK: # %bb.0: # %entry
92-
; CHECK-NEXT: la 3, a1[TD](2)
93-
; CHECK-NEXT: blr
132+
; CHECK: # %bb.0: # %entry
133+
; CHECK-NEXT: la 3, a1[TD](2)
134+
; CHECK-NEXT: blr
135+
;
136+
; CHECK-64-LABEL: escape2:
137+
; CHECK-64: # %bb.0: # %entry
138+
; CHECK-64-NEXT: la 3, a1[TD](2)
139+
; CHECK-64-NEXT: blr
94140
entry:
95141
ret ptr @a1
96142
}
97143

98144
define nonnull ptr @escape3() {
99145
; CHECK-LABEL: escape3:
100-
; CHECK: # %bb.0: # %entry
101-
; CHECK-NEXT: [[INSTR]] 3, L..C0(2) # @a4
102-
; CHECK-NEXT: blr
146+
; CHECK: # %bb.0: # %entry
147+
; CHECK-NEXT: lwz 3, L..C0(2) # @a4
148+
; CHECK-NEXT: blr
149+
;
150+
; CHECK-64-LABEL: escape3:
151+
; CHECK-64: # %bb.0: # %entry
152+
; CHECK-64-NEXT: ld 3, L..C0(2) # @a4
153+
; CHECK-64-NEXT: blr
103154
entry:
104155
ret ptr @a4
105156
}
106157

107158
define nonnull ptr @escape4() {
108159
; CHECK-LABEL: escape4:
109-
; CHECK: # %bb.0: # %entry
110-
; CHECK-NEXT: [[INSTR]] 3, L..C1(2) # @a3
111-
; CHECK-NEXT: blr
160+
; CHECK: # %bb.0: # %entry
161+
; CHECK-NEXT: lwz 3, L..C1(2) # @a3
162+
; CHECK-NEXT: blr
163+
;
164+
; CHECK-64-LABEL: escape4:
165+
; CHECK-64: # %bb.0: # %entry
166+
; CHECK-64-NEXT: ld 3, L..C1(2) # @a3
167+
; CHECK-64-NEXT: blr
112168
entry:
113169
ret ptr @a3
114170
}

‎llvm/test/CodeGen/PowerPC/toc-data.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -36,20 +36,20 @@ define dso_local void @write_int(i32 signext %in) {
3636
ret void
3737
}
3838
; CHECK32: name: write_int
39-
; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @i, $r2
39+
; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc $r2, @i
4040
; CHECK32-NEXT: STW %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
4141

4242
; TEST32: .write_int:
4343
; TEST32: la 4, i[TD](2)
4444
; TEST32-NEXT: stw 3, 0(4)
4545

4646
; CHECK64: name: write_int
47-
; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
47+
; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @i
4848
; CHECK64-NEXT: STW8 %{{[0-9]+}}, 0, killed %[[SCRATCH]] :: (store (s32) into @i)
4949

5050
; CHECK64-NOOPT: name: write_int
5151
; CHECK64-NOOPT: %[[SUBREG:[0-9]+]]:gprc = COPY %{{[0-9]}}.sub_32
52-
; CHECK64-NOOPT: %[[ADDR:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
52+
; CHECK64-NOOPT: %[[ADDR:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @i
5353
; CHECK64-NOOPT: STW %[[SUBREG]], 0, %[[ADDR]]
5454

5555
; TEST64: .write_int:
@@ -128,19 +128,19 @@ define dso_local float @read_float() {
128128
ret float %0
129129
}
130130
; CHECK32: name: read_float
131-
; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc @f, $r2
131+
; CHECK32: %[[SCRATCH:[0-9]+]]:gprc_and_gprc_nor0 = ADDItoc $r2, @f
132132
; CHECK32: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
133133

134134
; TEST32: .read_float:
135135
; TEST32: la 3, f[TD](2)
136136
; TEST32-NEXT: lfs 1, 0(3)
137137

138138
; CHECK64: name: read_float
139-
; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
139+
; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @f
140140
; CHECK64: %{{[0-9]+}}:f4rc = LFS 0, killed %[[SCRATCH]] :: (dereferenceable load (s32) from @f)
141141

142142
; CHECK64-NOOPT: name: read_float
143-
; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @f, $x2
143+
; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @f
144144
; CHECK64-NOOPT: %{{[0-9]+}}:f4rc = LFS 0, %[[SCRATCH]]
145145

146146
; TEST64: .read_float:
@@ -217,18 +217,18 @@ define dso_local nonnull ptr @addr() {
217217
ret ptr @i
218218
}
219219
; CHECK32: name: addr
220-
; CHECK32: %[[SCRATCH:[0-9]+]]:gprc = ADDItoc @i, $r2
220+
; CHECK32: %[[SCRATCH:[0-9]+]]:gprc = ADDItoc $r2, @i
221221
; CHECK32-NEXT: $r3 = COPY %[[SCRATCH]]
222222

223223
; TEST32: .addr
224224
; TEST32: la 3, i[TD](2)
225225

226226
; CHECK64: name: addr
227-
; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 @i, $x2
227+
; CHECK64: %[[SCRATCH:[0-9]+]]:g8rc = ADDItoc8 $x2, @i
228228
; CHECK64-NEXT: $x3 = COPY %[[SCRATCH]]
229229

230230
; CHECK64-NOOPT: name: addr
231-
; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 @i, $x2
231+
; CHECK64-NOOPT: %[[SCRATCH:[0-9]+]]:g8rc_and_g8rc_nox0 = ADDItoc8 $x2, @i
232232
; CHECK64-NOOPT: $x3 = COPY %[[SCRATCH]]
233233

234234
; TEST64: .addr

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