[ARM] Make sure we don't transform unaligned store to stm on Thumb1.

This isn't likely to come up in practice; the combination of compiler
flags required to hit this issue should be rare. Found by inspection.

Author: efriedma-quic

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -18169,6 +18169,8 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
     auto *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1));
     if (!RHS || RHS->getZExtValue() != 4)
       return false;
+    if (Alignment < Align(4))
+      return false;
 
     Offset = Op->getOperand(1);
     Base = Op->getOperand(0);

llvm/test/CodeGen/Thumb/ldm-stm-postinc.ll

@@ -79,3 +79,23 @@ define void @j(i32* %a, i32* readnone %b) {
 ._crit_edge:                                      ; preds = %.lr.ph, %0
   ret void
 }
+
+; Make sure we don't transform str->stm when unaligned loads are allowed.
+; CHECK-LABEL: @nostrictalign
+; CHECK: str r2, [r0]
+define void @nostrictalign(i32* %a, i32* readnone %b) "target-features"="-strict-align" {
+  %1 = icmp eq i32* %a, %b
+  br i1 %1, label %._crit_edge, label %.lr.ph
+
+.lr.ph:                                           ; preds = %.lr.ph, %0
+  %i.02 = phi i32 [ %2, %.lr.ph ], [ 0, %0 ]
+  %.01 = phi i32* [ %3, %.lr.ph ], [ %a, %0 ]
+  %2 = add nsw i32 %i.02, 1
+  store i32 %i.02, i32* %.01, align 1
+  %3 = getelementptr inbounds i32, i32* %.01, i32 1
+  %4 = icmp eq i32* %3, %b
+  br i1 %4, label %._crit_edge, label %.lr.ph
+
+._crit_edge:                                      ; preds = %.lr.ph, %0
+  ret void
+}