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[RISCV] Combine HasStdExtZfhOrZfhmin and HasStdExtZfhmin. NFC
I kept the AssemblerPredicate and diagnostic from HasStdExtZfhOrZfhmin that mentions both extensions, but replaced all uses with HasStdExtZfhmin. Same for the Zhinxmin equivalent.
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-36
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2 files changed

+26
-36
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‎llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -125,6 +125,7 @@ def FeatureStdExtZfhmin
125125
[FeatureStdExtF]>;
126126
def HasStdExtZfhmin : Predicate<"Subtarget->hasStdExtZfhmin()">,
127127
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
128+
"'Zfh' (Half-Precision Floating-Point) or "
128129
"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
129130

130131
def FeatureStdExtZfh
@@ -136,12 +137,6 @@ def HasStdExtZfh : Predicate<"Subtarget->hasStdExtZfh()">,
136137
"'Zfh' (Half-Precision Floating-Point)">;
137138
def NoStdExtZfh : Predicate<"!Subtarget->hasStdExtZfh()">;
138139

139-
def HasStdExtZfhOrZfhmin
140-
: Predicate<"Subtarget->hasStdExtZfhmin()">,
141-
AssemblerPredicate<(all_of FeatureStdExtZfhmin),
142-
"'Zfh' (Half-Precision Floating-Point) or "
143-
"'Zfhmin' (Half-Precision Floating-Point Minimal)">;
144-
145140
def FeatureStdExtZfinx
146141
: SubtargetFeature<"zfinx", "HasStdExtZfinx", "true",
147142
"'Zfinx' (Float in Integer)",
@@ -164,6 +159,7 @@ def FeatureStdExtZhinxmin
164159
[FeatureStdExtZfinx]>;
165160
def HasStdExtZhinxmin : Predicate<"Subtarget->hasStdExtZhinxmin()">,
166161
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
162+
"'Zhinx' (Half Float in Integer) or "
167163
"'Zhinxmin' (Half Float in Integer Minimal)">;
168164

169165
def FeatureStdExtZhinx
@@ -175,12 +171,6 @@ def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
175171
"'Zhinx' (Half Float in Integer)">;
176172
def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
177173

178-
def HasStdExtZhinxOrZhinxmin
179-
: Predicate<"Subtarget->hasStdExtZhinxmin()">,
180-
AssemblerPredicate<(all_of FeatureStdExtZhinxmin),
181-
"'Zhinx' (Half Float in Integer) or "
182-
"'Zhinxmin' (Half Float in Integer Minimal)">;
183-
184174
def FeatureStdExtZfa
185175
: SubtargetFeature<"zfa", "HasStdExtZfa", "true",
186176
"'Zfa' (Additional Floating-Point)",

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -40,30 +40,30 @@ def FPR16INX : RegisterOperand<GPRF16> {
4040

4141
def ZfhExt : ExtInfo<"", "", [HasStdExtZfh],
4242
f16, FPR16, FPR32, ?, FPR16>;
43-
def ZfhminExt : ExtInfo<"", "", [HasStdExtZfhOrZfhmin],
43+
def ZfhminExt : ExtInfo<"", "", [HasStdExtZfhmin],
4444
f16, FPR16, FPR32, ?, FPR16>;
4545
def ZfhDExt : ExtInfo<"", "", [HasStdExtZfh, HasStdExtD],
4646
?, ?, FPR32, FPR64, FPR16>;
47-
def ZfhminDExt : ExtInfo<"", "", [HasStdExtZfhOrZfhmin, HasStdExtD],
47+
def ZfhminDExt : ExtInfo<"", "", [HasStdExtZfhmin, HasStdExtD],
4848
?, ?, FPR32, FPR64, FPR16>;
4949

5050
def ZhinxExt : ExtInfo<"_INX", "RVZfinx",
5151
[HasStdExtZhinx],
5252
f16, FPR16INX, FPR32INX, ?, FPR16INX>;
5353
def ZhinxminExt : ExtInfo<"_INX", "RVZfinx",
54-
[HasStdExtZhinxOrZhinxmin],
54+
[HasStdExtZhinxmin],
5555
f16, FPR16INX, FPR32INX, ?, FPR16INX>;
5656
def ZhinxZdinxExt : ExtInfo<"_INX", "RVZfinx",
5757
[HasStdExtZhinx, HasStdExtZdinx, IsRV64],
5858
?, ?, FPR32INX, FPR64INX, FPR16INX>;
5959
def ZhinxminZdinxExt : ExtInfo<"_INX", "RVZfinx",
60-
[HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64],
60+
[HasStdExtZhinxmin, HasStdExtZdinx, IsRV64],
6161
?, ?, FPR32INX, FPR64INX, FPR16INX>;
6262
def ZhinxZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx",
6363
[HasStdExtZhinx, HasStdExtZdinx, IsRV32],
6464
?, ?, FPR32INX, FPR64IN32X, FPR16INX >;
6565
def ZhinxminZdinx32Ext : ExtInfo<"_IN32X", "RV32Zdinx",
66-
[HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32],
66+
[HasStdExtZhinxmin, HasStdExtZdinx, IsRV32],
6767
?, ?, FPR32INX, FPR64IN32X, FPR16INX>;
6868

6969
defvar ZfhExts = [ZfhExt, ZhinxExt];
@@ -200,10 +200,10 @@ foreach Ext = ZfhminDExts in {
200200
// Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
201201
//===----------------------------------------------------------------------===//
202202

203-
let Predicates = [HasStdExtZfhOrZfhmin] in {
203+
let Predicates = [HasStdExtZfhmin] in {
204204
def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>;
205205
def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
206-
} // Predicates = [HasStdExtZfhOrZfhmin]
206+
} // Predicates = [HasStdExtZfhmin]
207207

208208
let Predicates = [HasStdExtZfh] in {
209209
def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H FPR16:$rd, FPR16:$rs, FPR16:$rs)>;
@@ -223,10 +223,10 @@ def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;
223223
}
224224
} // Predicates = [HasStdExtZfh]
225225

226-
let Predicates = [HasStdExtZfhOrZfhmin] in {
226+
let Predicates = [HasStdExtZfhmin] in {
227227
def PseudoFLH : PseudoFloatLoad<"flh", FPR16>;
228228
def PseudoFSH : PseudoStore<"fsh", FPR16>;
229-
} // Predicates = [HasStdExtZfhOrZfhmin]
229+
} // Predicates = [HasStdExtZfhmin]
230230

231231
let Predicates = [HasStdExtZhinx] in {
232232
def : InstAlias<"fmv.h $rd, $rs", (FSGNJ_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
@@ -242,7 +242,7 @@ let usesCustomInserter = 1 in {
242242
def PseudoQuietFLE_H_INX : PseudoQuietFCMP<FPR16INX>;
243243
def PseudoQuietFLT_H_INX : PseudoQuietFCMP<FPR16INX>;
244244
}
245-
} // Predicates = [HasStdExtZhinxOrZhinxmin]
245+
} // Predicates = [HasStdExtZhinxmin]
246246

247247
//===----------------------------------------------------------------------===//
248248
// Pseudo-instructions and codegen patterns
@@ -412,15 +412,15 @@ defm Select_FPR16INX : SelectCC_GPR_rrirr<FPR16INX, f16>;
412412
def PseudoFROUND_H_INX : PseudoFROUND<FPR16INX, f16>;
413413
} // Predicates = [HasStdExtZhinx]
414414

415-
let Predicates = [HasStdExtZfhOrZfhmin] in {
415+
let Predicates = [HasStdExtZfhmin] in {
416416
/// Loads
417417
def : LdPat<load, FLH, f16>;
418418

419419
/// Stores
420420
def : StPat<store, FSH, FPR16, f16>;
421-
} // Predicates = [HasStdExtZfhOrZfhmin]
421+
} // Predicates = [HasStdExtZfhmin]
422422

423-
let Predicates = [HasStdExtZhinxOrZhinxmin] in {
423+
let Predicates = [HasStdExtZhinxmin] in {
424424
/// Loads
425425
def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
426426
(COPY_TO_REGCLASS (LH GPR:$rs1, simm12:$imm12), GPRF16)>;
@@ -429,9 +429,9 @@ def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
429429
def : Pat<(store (f16 FPR16INX:$rs2),
430430
(AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12)),
431431
(SH (COPY_TO_REGCLASS FPR16INX:$rs2, GPR), GPR:$rs1, simm12:$imm12)>;
432-
} // Predicates = [HasStdExtZhinxOrZhinxmin]
432+
} // Predicates = [HasStdExtZhinxmin]
433433

434-
let Predicates = [HasStdExtZfhOrZfhmin] in {
434+
let Predicates = [HasStdExtZfhmin] in {
435435
/// Float conversion operations
436436

437437
// f32 -> f16, f16 -> f32
@@ -444,9 +444,9 @@ def : Pat<(riscv_fmv_x_anyexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
444444
def : Pat<(riscv_fmv_x_signexth (f16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
445445

446446
def : Pat<(fcopysign FPR32:$rs1, (f16 FPR16:$rs2)), (FSGNJ_S $rs1, (FCVT_S_H $rs2, FRM_RNE))>;
447-
} // Predicates = [HasStdExtZfhOrZfhmin]
447+
} // Predicates = [HasStdExtZfhmin]
448448

449-
let Predicates = [HasStdExtZhinxOrZhinxmin] in {
449+
let Predicates = [HasStdExtZhinxmin] in {
450450
/// Float conversion operations
451451

452452
// f32 -> f16, f16 -> f32
@@ -459,7 +459,7 @@ def : Pat<(riscv_fmv_x_anyexth FPR16INX:$src), (COPY_TO_REGCLASS FPR16INX:$src,
459459
def : Pat<(riscv_fmv_x_signexth FPR16INX:$src), (COPY_TO_REGCLASS FPR16INX:$src, GPR)>;
460460

461461
def : Pat<(fcopysign FPR32INX:$rs1, FPR16INX:$rs2), (FSGNJ_S_INX $rs1, (FCVT_S_H_INX $rs2, FRM_RNE))>;
462-
} // Predicates = [HasStdExtZhinxOrZhinxmin]
462+
} // Predicates = [HasStdExtZhinxmin]
463463

464464
let Predicates = [HasStdExtZfh] in {
465465
// half->[u]int. Round-to-zero must be used.
@@ -561,7 +561,7 @@ def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L_INX $rs1, FRM_DYN)>;
561561
def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU_INX $rs1, FRM_DYN)>;
562562
} // Predicates = [HasStdExtZhinx, IsRV64]
563563

564-
let Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] in {
564+
let Predicates = [HasStdExtZfhmin, HasStdExtD] in {
565565
/// Float conversion operations
566566
// f64 -> f16, f16 -> f64
567567
def : Pat<(f16 (any_fpround FPR64:$rs1)), (FCVT_H_D FPR64:$rs1, FRM_DYN)>;
@@ -571,9 +571,9 @@ def : Pat<(any_fpextend (f16 FPR16:$rs1)), (FCVT_D_H FPR16:$rs1, FRM_RNE)>;
571571
def : Pat<(f16 (fcopysign FPR16:$rs1, FPR64:$rs2)),
572572
(FSGNJ_H $rs1, (FCVT_H_D $rs2, FRM_DYN))>;
573573
def : Pat<(fcopysign FPR64:$rs1, (f16 FPR16:$rs2)), (FSGNJ_D $rs1, (FCVT_D_H $rs2, FRM_RNE))>;
574-
} // Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD]
574+
} // Predicates = [HasStdExtZfhmin, HasStdExtD]
575575

576-
let Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32] in {
576+
let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32] in {
577577
/// Float conversion operations
578578
// f64 -> f16, f16 -> f64
579579
def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_H_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>;
@@ -583,9 +583,9 @@ def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_IN32X FPR16INX:$rs1, FRM_RNE)>
583583
def : Pat<(fcopysign FPR16INX:$rs1, FPR64IN32X:$rs2),
584584
(FSGNJ_H_INX $rs1, (FCVT_H_D_IN32X $rs2, 0b111))>;
585585
def : Pat<(fcopysign FPR64IN32X:$rs1, FPR16INX:$rs2), (FSGNJ_D_IN32X $rs1, (FCVT_D_H_IN32X $rs2, FRM_RNE))>;
586-
} // Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32]
586+
} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV32]
587587

588-
let Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64] in {
588+
let Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64] in {
589589
/// Float conversion operations
590590
// f64 -> f16, f16 -> f64
591591
def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_H_D_INX FPR64INX:$rs1, FRM_DYN)>;
@@ -595,7 +595,7 @@ def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_INX FPR16INX:$rs1, FRM_RNE)>;
595595
def : Pat<(fcopysign FPR16INX:$rs1, FPR64INX:$rs2),
596596
(FSGNJ_H_INX $rs1, (FCVT_H_D_INX $rs2, 0b111))>;
597597
def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (FCVT_D_H_INX $rs2, FRM_RNE))>;
598-
} // Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64]
598+
} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64]
599599

600600
let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
601601
// half->[u]int. Round-to-zero must be used.

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